AGH-engineering-thesis - Code related to my engineering thesis at AGH University of Science and Technology in Kraków, Poland

Age	Commit message (Collapse)	Author
2020-12-24	prepare makefile infrastructure for writing examples	Wojciech Kosior

2020-12-21	remove double lines in memory map comments	Wojciech Kosior

2020-11-23	write Wasm code, that can print a number on the screen	Wojciech Kosior

2020-11-23	add unsigned division remainder instruction	Wojciech Kosior

2020-11-21	add miscellaneous module, which controls led2 and button2 and provides a ↵	Wojciech Kosior
	timer; include a testbench for timer and led
2020-11-21	fix typo in comment	Wojciech Kosior

2020-11-21	increase number of wb slaves, that can be attached to the intercon	Wojciech Kosior

2020-11-03	incorporate SPI module into main design	Wojciech Kosior

2020-11-03	add spi wishbone slave with a simplified flash memory chip model and a test ↵	Wojciech Kosior
	bench
2020-10-10	fix yosys synthesis	Wojciech Kosior

2020-10-06	add some debugging facility inside the cpu	Wojciech Kosior

2020-10-06	add relational operations to stack machine	Wojciech Kosior

2020-10-05	fixes, add_sp instruciton and translation of br instruction from wasm	Wojciech Kosior

2020-10-05	fixes, conditional if-not jump and translation of if-else instruction from wasm	Wojciech Kosior

2020-09-16	add function calling (call, ret and drop instructions) with a testbench + ↵	Wojciech Kosior
	bugfix in stack machine
2020-09-16	also enable reading from vga text memory	Wojciech Kosior

2020-09-14	add ability to make non-aligned loads/stores and loads/stores of 1 or 2 ↵	Wojciech Kosior
	bytes together with test bench
2020-09-09	enable byte-grained reads and writes through interface_wrapper	Wojciech Kosior

2020-09-08	remove trailing whitespace	Wojciech Kosior

2020-09-08	use new machine's instructions in synthesis	Wojciech Kosior

2020-09-07	remove old version of stack machine from the project	Wojciech Kosior

2020-09-07	update soc toplevel module to use new version of stack machine	Wojciech Kosior

2020-09-07	add wrapped stack machine with bench	Wojciech Kosior

2020-09-07	add intercon module, that encapsulates slave_dispatcher and master_arbiter ↵	Wojciech Kosior
	and a bench for it (use adapted operations files from master_arbiter test)
2020-09-07	fix port directions	Wojciech Kosior

2020-09-07	rename intercon to slave_dispatcher (soc module will remporarily stop ↵	Wojciech Kosior
	working from this commit on)
2020-09-07	add a wishbone arbiter for 2 masters	Wojciech Kosior

2020-09-07	add wrapper from wb master interface with 32-bit data port to wb interface ↵	Wojciech Kosior
	with 16-bit data port together with testbench
2020-09-05	add cond_jump instruction together with bench	Wojciech Kosior

2020-09-05	add jump instruction together with bench	Wojciech Kosior

2020-09-05	add mul instruction together with bench	Wojciech Kosior

2020-09-05	add div instruction together with bench	Wojciech Kosior

2020-09-05	add swap instruction together with bench	Wojciech Kosior

2020-09-05	add sub instruction together with bench	Wojciech Kosior

2020-09-05	add add instruction together with bench	Wojciech Kosior

2020-09-05	add tee instruction together with bench	Wojciech Kosior

2020-09-05	start another attempt for good stack machine design	Wojciech Kosior

2020-09-03	rename tclasm.tcl to tclasm_old.tcl (prepare for redesign of the stack machine)	Wojciech Kosior

2020-09-03	rename stack_machine to stack_machine_old (prepare for redesign of the machine)	Wojciech Kosior

2020-09-03	add the ability to synthesize the design	Wojciech Kosior

2020-09-03	make embedded memory with program code read-only (not strictly needed, but ↵	Wojciech Kosior
	protects it from accidental overwriting before reset button is pressed)
2020-09-03	register values immediately after reading the from embedded ram (this is ↵	Wojciech Kosior
	required for memories to get inferred)
2020-09-02	add topmost module of the synthesizable design	Wojciech Kosior

2020-09-02	name correction: remove "wb" from "sram_wb_slave"	Wojciech Kosior

2020-09-02	add wishbone slave with embedded bram	Wojciech Kosior

2020-09-02	add wishbone wrapper for sram	Wojciech Kosior

2020-09-02	add tee instruction	Wojciech Kosior

2020-09-01	change horizontal counter initialization on reset	Wojciech Kosior

2020-09-01	whenever we have a big array, signify, that we're using embedded RAM for it	Wojciech Kosior

2020-09-01	start anew	Wojciech Kosior