update soc toplevel module to use new version of stack machine

1 files changed, 60 insertions, 48 deletions

diff --git a/design/soc.v b/design/soc.v
index 39cdde8..d4a5962 100644
--- a/design/soc.v
+++ b/design/soc.v
@@ -29,7 +29,7 @@ module soc
     )
    (
     input wire 	       clock_100mhz,
-   
+
     output wire [17:0] sram_addr,
     inout wire [15:0]  sram_io,
 
@@ -50,23 +50,23 @@ module soc
     output wire        led2
    );
 
-   wire 	       M_ACK_I;
-   wire 	       M_CLK_I;
-   wire [19:0] 	       M_ADR_O;
-   wire [15:0] 	       M_DAT_I;
-   wire [15:0] 	       M_DAT_O;
-   wire 	       M_RST_I;
-   wire 	       M_STB_O;
-   wire 	       M_CYC_O;
-   wire 	       M_WE_O;
-   wire 	       M_STALL_I;
+   /*
+    * Master 0 is stack machine's wrapped data interface.
+    * Master 1 is stack machine's instructions interface.
+    */
+   wire        M0_ACK_I,   M1_ACK_I;
+   wire [19:0] M0_ADR_O,   M1_ADR_O;
+   wire [15:0] M0_DAT_I,   M1_DAT_I;
+   wire [15:0] M0_DAT_O,   M1_DAT_O;
+   wire        M0_STB_O,   M1_STB_O;
+   wire        M0_CYC_O,   M1_CYC_O;
+   wire        M0_WE_O,    M1_WE_O;
+   wire        M0_STALL_I, M1_STALL_I;
 
    wire 	       S0_ACK_O,   S1_ACK_O,   S2_ACK_O,   S3_ACK_O;
-   wire 	       S0_CLK_I,   S1_CLK_I,   S2_CLK_I,   S3_CLK_I;
    wire [17:0] 	       S0_ADR_I,   S1_ADR_I,   S2_ADR_I,   S3_ADR_I;
    wire [15:0] 	       S0_DAT_I,   S1_DAT_I,   S2_DAT_I,   S3_DAT_I;
    wire [15:0] 	       S0_DAT_O,   S1_DAT_O,   S2_DAT_O,   S3_DAT_O;
-   wire 	       S0_RST_I,   S1_RST_I,   S2_RST_I,   S3_RST_I;
    wire 	       S0_STB_I,   S1_STB_I,   S2_STB_I,   S3_STB_I;
    wire 	       S0_WE_I,    S1_WE_I,    S2_WE_I,    S3_WE_I;
    wire 	       S0_STALL_O, S1_STALL_O, S2_STALL_O, S3_STALL_O;
@@ -79,18 +79,30 @@ module soc
    wire 	       clock_25mhz;
 
 
-   stack_machine stack_machine
+   wrapped_stack_machine stack_machine
      (
-      .ACK_I(M_ACK_I),
-      .CLK_I(M_CLK_I),
-      .ADR_O(M_ADR_O),
-      .DAT_I(M_DAT_I),
-      .DAT_O(M_DAT_O),
-      .RST_I(M_RST_I),
-      .STB_O(M_STB_O),
-      .CYC_O(M_CYC_O),
-      .WE_O(M_WE_O),
-      .STALL_I(M_STALL_I),
+      .CLK_I(CLK),
+      .RST_I(RST),
+
+      /* Instruction reading interface */
+      .I_ACK_I(M1_ACK_I),
+      .I_ADR_O(M1_ADR_O),
+      .I_DAT_I(M1_DAT_I),
+      .I_DAT_O(M1_DAT_O),
+      .I_STB_O(M1_STB_O),
+      .I_CYC_O(M1_CYC_O),
+      .I_WE_O(M1_WE_O),
+      .I_STALL_I(M1_STALL_I),
+
+      /* Data interface */
+      .D_ACK_I(M0_ACK_I),
+      .D_ADR_O(M0_ADR_O),
+      .D_DAT_I(M0_DAT_I),
+      .D_DAT_O(M0_DAT_O),
+      .D_STB_O(M0_STB_O),
+      .D_CYC_O(M0_CYC_O),
+      .D_WE_O(M0_WE_O),
+      .D_STALL_I(M0_STALL_I),
 
       .finished(M_finished)
       );
@@ -103,11 +115,11 @@ module soc
        ) slave0
        (
 	.ACK_O(S0_ACK_O),
-      	.CLK_I(S0_CLK_I),
+      	.CLK_I(CLK),
 	.ADR_I(S0_ADR_I[7:0]),
 	.DAT_I(S0_DAT_I),
 	.DAT_O(S0_DAT_O),
-      	.RST_I(S0_RST_I),
+      	.RST_I(RST),
       	.STB_I(S0_STB_I),
       	.WE_I(S0_WE_I),
 	.STALL_O(S0_STALL_O)
@@ -122,11 +134,11 @@ module soc
       .sram_we_n(sram_we_n),
 
       .ACK_O(S1_ACK_O),
-      .CLK_I(S1_CLK_I),
+      .CLK_I(CLK),
       .ADR_I(S1_ADR_I),
       .DAT_I(S1_DAT_I),
       .DAT_O(S1_DAT_O),
-      .RST_I(S1_RST_I),
+      .RST_I(RST),
       .STB_I(S1_STB_I),
       .WE_I(S1_WE_I),
       .STALL_O(S1_STALL_O)
@@ -138,11 +150,11 @@ module soc
        ) slave2
        (
 	.ACK_O(S2_ACK_O),
-      	.CLK_I(S2_CLK_I),
+      	.CLK_I(CLK),
 	.ADR_I(S2_ADR_I[10:0]),
 	.DAT_I(S2_DAT_I),
 	.DAT_O(S2_DAT_O),
-      	.RST_I(S2_RST_I),
+      	.RST_I(RST),
       	.STB_I(S2_STB_I),
       	.WE_I(S2_WE_I),
 	.STALL_O(S2_STALL_O),
@@ -167,55 +179,54 @@ module soc
       .RST(RST),
 
       .S0_ACK_O(S0_ACK_O),
-      .S0_CLK_I(S0_CLK_I),
       .S0_ADR_I(S0_ADR_I),
       .S0_DAT_I(S0_DAT_I),
       .S0_DAT_O(S0_DAT_O),
-      .S0_RST_I(S0_RST_I),
       .S0_STB_I(S0_STB_I),
       .S0_WE_I(S0_WE_I),
       .S0_STALL_O(S0_STALL_O),
 
       .S1_ACK_O(S1_ACK_O),
-      .S1_CLK_I(S1_CLK_I),
       .S1_ADR_I(S1_ADR_I),
       .S1_DAT_I(S1_DAT_I),
       .S1_DAT_O(S1_DAT_O),
-      .S1_RST_I(S1_RST_I),
       .S1_STB_I(S1_STB_I),
       .S1_WE_I(S1_WE_I),
       .S1_STALL_O(S1_STALL_O),
 
       .S2_ACK_O(S2_ACK_O),
-      .S2_CLK_I(S2_CLK_I),
       .S2_ADR_I(S2_ADR_I),
       .S2_DAT_I(S2_DAT_I),
       .S2_DAT_O(S2_DAT_O),
-      .S2_RST_I(S2_RST_I),
       .S2_STB_I(S2_STB_I),
       .S2_WE_I(S2_WE_I),
       .S2_STALL_O(S2_STALL_O),
 
       .S3_ACK_O(S3_ACK_O),
-      .S3_CLK_I(S3_CLK_I),
       .S3_ADR_I(S3_ADR_I),
       .S3_DAT_I(S3_DAT_I),
       .S3_DAT_O(S3_DAT_O),
-      .S3_RST_I(S3_RST_I),
       .S3_STB_I(S3_STB_I),
       .S3_WE_I(S3_WE_I),
       .S3_STALL_O(S3_STALL_O),
 
-      .M_ACK_I(M_ACK_I),
-      .M_CLK_I(M_CLK_I),
-      .M_ADR_O(M_ADR_O),
-      .M_DAT_O(M_DAT_O),
-      .M_DAT_I(M_DAT_I),
-      .M_RST_I(M_RST_I),
-      .M_STB_O(M_STB_O),
-      .M_CYC_O(M_CYC_O),
-      .M_WE_O(M_WE_O),
-      .M_STALL_I(M_STALL_I)
+      .M0_ACK_I(M0_ACK_I),
+      .M0_ADR_O(M0_ADR_O),
+      .M0_DAT_I(M0_DAT_I),
+      .M0_DAT_O(M0_DAT_O),
+      .M0_STB_O(M0_STB_O),
+      .M0_CYC_O(M0_CYC_O),
+      .M0_WE_O(M0_WE_O),
+      .M0_STALL_I(M0_STALL_I),
+
+      .M1_ACK_I(M1_ACK_I),
+      .M1_ADR_O(M1_ADR_O),
+      .M1_DAT_I(M1_DAT_I),
+      .M1_DAT_O(M1_DAT_O),
+      .M1_STB_O(M1_STB_O),
+      .M1_CYC_O(M1_CYC_O),
+      .M1_WE_O(M1_WE_O),
+      .M1_STALL_I(M1_STALL_I)
       );
 
    reg [2:0] 	       clock_divider;
@@ -223,6 +234,7 @@ module soc
      clock_divider <= clock_divider + 1;
 
    assign clock_25mhz = clock_divider[1];
+   /* We might later raise it up to even as high as 50 MHz */
    assign CLK = clock_divider[2];
 
    reg 		       reset;