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| author | Wojciech Kosior <kwojtus@protonmail.com> | 2020-09-05 17:09:16 +0200 |
|---|---|---|
| committer | Wojciech Kosior <kwojtus@protonmail.com> | 2020-09-05 17:09:16 +0200 |
| commit | ba4d97ddc2133c905e668c2f916cf3b14be4e35d (patch) | |
| tree | 68dec077eeea05aef51ed0172a16c100c57b9e54 /design | |
| parent | 3ec21a949b0887e32bbffcdb38a5738abfe8cfd0 (diff) | |
| download | AGH-engineering-thesis-ba4d97ddc2133c905e668c2f916cf3b14be4e35d.tar.gz AGH-engineering-thesis-ba4d97ddc2133c905e668c2f916cf3b14be4e35d.zip | |
add sub instruction together with bench
Diffstat (limited to 'design')
| -rw-r--r-- | design/stack_machine.v | 10 |
1 files changed, 9 insertions, 1 deletions
diff --git a/design/stack_machine.v b/design/stack_machine.v index d79a136..868a103 100644 --- a/design/stack_machine.v +++ b/design/stack_machine.v @@ -200,6 +200,11 @@ module stack_machine_new assign instr_add = !set_im && !use_im && stack_shrinks_by_1 && instruction[11:0] == 12'd0; + wire instr_sub; + assign instr_sub = !set_im && !use_im && stack_shrinks_by_1 && + instruction[11:0] == 12'd1; + + reg halt; /* Set once a halt instruction is encountered */ assign finished = halt; @@ -446,7 +451,10 @@ module stack_machine_new /* Instructions, that shrink stack */ if (instr_add && first_execution_tick) - r1 <= r1 + r0; + r1 <= r0 + r1; + + if (instr_sub && first_execution_tick) + r1 <= r0 - r1; end // case: STEP_EXECUTING endcase // case (step) end // else: !if(RST_I) |