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author | Wojciech Kosior <kwojtus@protonmail.com> | 2020-09-08 17:46:12 +0200 |
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committer | Wojciech Kosior <kwojtus@protonmail.com> | 2020-09-08 17:46:12 +0200 |
commit | cd0421f0c30fcbe557c89f0fe7cd1b1e5ea42f9c (patch) | |
tree | feb49818e92940cd20586dcb23951fe04e54a2f2 /design | |
parent | dfcd082cd2290fb39d8cb322f2ab70f0e8752ef7 (diff) | |
download | AGH-engineering-thesis-cd0421f0c30fcbe557c89f0fe7cd1b1e5ea42f9c.tar.gz AGH-engineering-thesis-cd0421f0c30fcbe557c89f0fe7cd1b1e5ea42f9c.zip |
remove trailing whitespace
Diffstat (limited to 'design')
-rw-r--r-- | design/div.v | 2 | ||||
-rw-r--r-- | design/vga.v | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/design/div.v b/design/div.v index 10db627..42c7a1e 100644 --- a/design/div.v +++ b/design/div.v @@ -25,7 +25,7 @@ module div wire work_remainder_sign; assign work_remainder = work_reg[2*WIDTH : WIDTH-1]; assign work_remainder_sign = work_remainder[WIDTH + 1]; - + /* * The following variable represents quotient using digits 1 and -1, * where -1 is internally represented as 0 diff --git a/design/vga.v b/design/vga.v index b46dcbd..05a5c60 100644 --- a/design/vga.v +++ b/design/vga.v @@ -141,7 +141,7 @@ v_counter <= 0; end else begin // if ((v_stage == V_STAGE_BB_OR_FP &&... v_counter <= v_counter + 1; - end + end end // if (end_of_line) end else begin // if (powered_on_latched) v_stage <= V_STAGE_BB_OR_FP; |