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authorWojciech Kosior <kwojtus@protonmail.com>2020-09-16 14:39:57 +0200
committerWojciech Kosior <kwojtus@protonmail.com>2020-09-16 14:39:57 +0200
commit196582e9c74cbdc02e66189774ed22f2ca632691 (patch)
tree3cbcdf5b5006c8b0bf244a6dda7acf30c8527e39 /design
parent39d5fca054a6790918b4774afbb4d4b753470ea9 (diff)
downloadAGH-engineering-thesis-196582e9c74cbdc02e66189774ed22f2ca632691.tar.gz
AGH-engineering-thesis-196582e9c74cbdc02e66189774ed22f2ca632691.zip
also enable reading from vga text memory
Diffstat (limited to 'design')
-rw-r--r--design/vga.v13
1 files changed, 8 insertions, 5 deletions
diff --git a/design/vga.v b/design/vga.v
index 05a5c60..e69907c 100644
--- a/design/vga.v
+++ b/design/vga.v
@@ -38,14 +38,13 @@
*/
reg [15:0] text_memory [1279 : 0];
- /*
- * Enable writes to text_memory using wishbone interface.
- * (no reads for now)
- */
+ /* Enable writes and reads of text_memory using wishbone interface. */
+ reg [15:0] data_at_adr;
+ reg outputting_data;
reg ack;
- assign DAT_O = {16{powered_on}};
+ assign DAT_O = outputting_data ? data_at_adr : {16{powered_on}};
assign ACK_O = ack;
assign STALL_O = 1'b0;
@@ -58,6 +57,10 @@
else
powered_on <= DAT_I != 16'b0;
end
+
+ outputting_data <= ADR_I < 1280;
+
+ data_at_adr <= text_memory[ADR_I];
end
/* Non-wishbone part - generate 640x480 60Hz VGA output */