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authorWojciech Kosior <kwojtus@protonmail.com>2020-09-03 17:40:53 +0200
committerWojciech Kosior <kwojtus@protonmail.com>2020-09-03 17:40:53 +0200
commit3c7da9cdf1e69a6a0a64cb99ddbf2d0695000391 (patch)
tree59daae3c107c6bca19473f33cf8a0524888653e7 /design
parentd39bdc0782ce5dcfc422ddb613f6af1953f664c0 (diff)
downloadAGH-engineering-thesis-3c7da9cdf1e69a6a0a64cb99ddbf2d0695000391.tar.gz
AGH-engineering-thesis-3c7da9cdf1e69a6a0a64cb99ddbf2d0695000391.zip
make embedded memory with program code read-only (not strictly needed, but protects it from accidental overwriting before reset button is pressed)
Diffstat (limited to 'design')
-rw-r--r--design/embedded_bram_slave.v10
1 files changed, 6 insertions, 4 deletions
diff --git a/design/embedded_bram_slave.v b/design/embedded_bram_slave.v
index 17738af..3829316 100644
--- a/design/embedded_bram_slave.v
+++ b/design/embedded_bram_slave.v
@@ -30,6 +30,11 @@ module embedded_bram_slave
if (WORDS_TO_INITIALIZE) begin
initial
$readmemb(INITIAL_CONTENTS_FILE, memory, 0, WORDS_TO_INITIALIZE - 1);
+ end else begin
+ always @ (posedge CLK_I) begin
+ if (!RST_I && STB_I && WE_I)
+ memory[ADR_I] <= DAT_I;
+ end
end
endgenerate
@@ -47,9 +52,6 @@ module embedded_bram_slave
ack <= STB_I;
output_data <= memory[ADR_I];
-
- if (STB_I && WE_I)
- memory[ADR_I] <= DAT_I;
end
- end // always @ (posedge CLK_I)
+ end
endmodule // embedded_bram_slave