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| author | Wojciech Kosior <kwojtus@protonmail.com> | 2020-09-01 16:42:49 +0200 |
|---|---|---|
| committer | Wojciech Kosior <kwojtus@protonmail.com> | 2020-09-01 16:42:49 +0200 |
| commit | 5019472722421910d763fcbdda5541272c25a96f (patch) | |
| tree | 7488bfc00c1cd7747476a34daa6839681612c79b /design | |
| parent | fc243554a125cb53af0bdf4aa76f95e6c6419e48 (diff) | |
| download | AGH-engineering-thesis-5019472722421910d763fcbdda5541272c25a96f.tar.gz AGH-engineering-thesis-5019472722421910d763fcbdda5541272c25a96f.zip | |
change horizontal counter initialization on reset
Diffstat (limited to 'design')
| -rw-r--r-- | design/vga.v | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/design/vga.v b/design/vga.v index 9057304..e652ea6 100644 --- a/design/vga.v +++ b/design/vga.v @@ -101,7 +101,7 @@ end end else begin // if (powered_on_latched) h_stage <= H_STAGE_RB_OR_FP; - h_counter <= H_RIGHT_BORDER; + h_counter <= H_RIGHT_BORDER - 1; end // else: !if(powered_on_latched) end // always @ (posedge clock_25mhz) |