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| author | Wojciech Kosior <kwojtus@protonmail.com> | 2020-09-05 18:21:53 +0200 |
|---|---|---|
| committer | Wojciech Kosior <kwojtus@protonmail.com> | 2020-09-05 18:21:53 +0200 |
| commit | 8d92524d4c46493ad83ebd493dabd3f88e11037b (patch) | |
| tree | 62973748aa831b2b64241d5a8b27565abdc707c8 /design | |
| parent | 2c528314ebe29a1c94b6c03fd1b0e2668ee25dff (diff) | |
| download | AGH-engineering-thesis-8d92524d4c46493ad83ebd493dabd3f88e11037b.tar.gz AGH-engineering-thesis-8d92524d4c46493ad83ebd493dabd3f88e11037b.zip | |
add mul instruction together with bench
Diffstat (limited to 'design')
| -rw-r--r-- | design/stack_machine.v | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/design/stack_machine.v b/design/stack_machine.v index 4313713..a6b2765 100644 --- a/design/stack_machine.v +++ b/design/stack_machine.v @@ -212,6 +212,10 @@ module stack_machine_new assign instr_udiv = !set_im && !use_im && stack_shrinks_by_1 && instruction[11:0] == 12'd2; + wire instr_mul; + assign instr_mul = !set_im && !use_im && stack_shrinks_by_1 && + instruction[11:0] == 12'd3; + reg halt; /* Set once a halt instruction is encountered */ assign finished = halt; @@ -505,6 +509,9 @@ module stack_machine_new if (instr_udiv && arithmetic_uncompleted) r1 <= div_quotient; + + if (instr_mul && arithmetic_uncompleted) + r1 <= r0 * r1; end // case: STEP_EXECUTING endcase // case (step) end // else: !if(RST_I) |