add wrapped stack machine with bench

1 files changed, 103 insertions, 0 deletions

diff --git a/design/wrapped_stack_machine.v b/design/wrapped_stack_machine.v
new file mode 100644
index 0000000..984b641
--- /dev/null
+++ b/design/wrapped_stack_machine.v
@@ -0,0 +1,103 @@
+/*
+ * This is a version of stack machine with 16-bit data ports
+ * on *both* wishbone interfaces (data interface is wrapped).
+ */
+`default_nettype none
+
+module wrapped_stack_machine
+  (
+   /* Those 2 are supposed to be common for both wishbone interfaces */
+   input wire 	      CLK_I,
+   input wire 	      RST_I,
+
+   /* Instruction reading interface */
+   input wire 	      I_ACK_I,
+   output wire [19:0] I_ADR_O,
+   input wire [15:0]  I_DAT_I,
+   output wire [15:0] I_DAT_O, /* Not used, interface read-only */
+   output wire 	      I_STB_O,
+   output wire 	      I_CYC_O,
+   output wire 	      I_WE_O, /* Always 0, interface read-only */
+   input wire 	      I_STALL_I,
+
+   /* Data interface */
+   input wire 	      D_ACK_I,
+   output wire [19:0] D_ADR_O,
+   input wire [15:0]  D_DAT_I,
+   output wire [15:0] D_DAT_O,
+   output wire 	      D_STB_O,
+   output wire 	      D_CYC_O,
+   output wire 	      D_WE_O,
+   input wire 	      D_STALL_I,
+
+   /* non-wishbone */
+   output wire 	      finished
+   );
+
+   wire 	      D_RAW_ACK_I;
+   wire 	      D_RAW_ERR_I; /* Not used yet, always low */
+   wire [20:0] 	      D_RAW_ADR_O;
+   wire [31:0] 	      D_RAW_DAT_I;
+   wire [31:0] 	      D_RAW_DAT_O;
+   wire [3:0] 	      D_RAW_SEL_O; /* Not used yet, always 4'hF */
+   wire 	      D_RAW_STB_O;
+   wire 	      D_RAW_CYC_O;
+   wire 	      D_RAW_WE_O;
+   wire 	      D_RAW_STALL_I;
+
+   stack_machine_new stack_machine
+     (
+      .CLK_I(CLK_I),
+      .RST_I(RST_I),
+
+      /* Instruction reading interface */
+      .I_ACK_I(I_ACK_I),
+      .I_ADR_O(I_ADR_O),
+      .I_DAT_I(I_DAT_I),
+      .I_DAT_O(I_DAT_O),
+      .I_STB_O(I_STB_O),
+      .I_CYC_O(I_CYC_O),
+      .I_WE_O(I_WE_O),
+      .I_STALL_I(I_STALL_I),
+
+      /* Data interface */
+      .D_ACK_I(D_RAW_ACK_I),
+      .D_ERR_I(D_RAW_ERR_I),
+      .D_ADR_O(D_RAW_ADR_O),
+      .D_DAT_I(D_RAW_DAT_I),
+      .D_DAT_O(D_RAW_DAT_O),
+      .D_SEL_O(D_RAW_SEL_O),
+      .D_STB_O(D_RAW_STB_O),
+      .D_CYC_O(D_RAW_CYC_O),
+      .D_WE_O(D_RAW_WE_O),
+      .D_STALL_I(D_RAW_STALL_I),
+
+      .finished(finished)
+      );
+
+   interface_wrapper wrapper
+     (
+      .CLK_I(CLK_I),
+      .RST_I(RST_I),
+
+      .RAW_ACK_I(D_RAW_ACK_I),
+      .RAW_ERR_I(D_RAW_ERR_I),
+      .RAW_ADR_O(D_RAW_ADR_O),
+      .RAW_DAT_I(D_RAW_DAT_I),
+      .RAW_DAT_O(D_RAW_DAT_O),
+      .RAW_SEL_O(D_RAW_SEL_O),
+      .RAW_STB_O(D_RAW_STB_O),
+      .RAW_CYC_O(D_RAW_CYC_O),
+      .RAW_WE_O(D_RAW_WE_O),
+      .RAW_STALL_I(D_RAW_STALL_I),
+
+      .WRAPPED_ACK_I(D_ACK_I),
+      .WRAPPED_ADR_O(D_ADR_O),
+      .WRAPPED_DAT_I(D_DAT_I),
+      .WRAPPED_DAT_O(D_DAT_O),
+      .WRAPPED_STB_O(D_STB_O),
+      .WRAPPED_CYC_O(D_CYC_O),
+      .WRAPPED_WE_O(D_WE_O),
+      .WRAPPED_STALL_I(D_STALL_I)
+      );
+endmodule // wrapped_stack_machine