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AGH-engineering-thesis
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Code related to my engineering thesis at AGH University of Science and Technology in Kraków, Poland
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2020-09-09
enable byte-grained reads and writes through interface_wrapper
Wojciech Kosior
2020-09-09
fix verification when SEL_O != 4'b1111
Wojciech Kosior
2020-09-08
enable slave and master models to use SEL_ signal
Wojciech Kosior
2020-09-08
remove trailing whitespace
Wojciech Kosior
2020-09-08
Update README
Wojciech Kosior
2020-09-08
modernize the build (test) system
Wojciech Kosior
2020-09-08
remove old debugging code
Wojciech Kosior
2020-09-08
use new machine's instructions in synthesis
Wojciech Kosior
2020-09-07
remove old version of stack machine from the project
Wojciech Kosior
2020-09-07
update soc toplevel module to use new version of stack machine
Wojciech Kosior
2020-09-07
add wrapped stack machine with bench
Wojciech Kosior
2020-09-07
add intercon module, that encapsulates slave_dispatcher and master_arbiter an...
Wojciech Kosior
2020-09-07
fix port directions
Wojciech Kosior
2020-09-07
rename intercon to slave_dispatcher (soc module will remporarily stop working...
Wojciech Kosior
2020-09-07
add a wishbone arbiter for 2 masters
Wojciech Kosior
2020-09-07
add wrapper from wb master interface with 32-bit data port to wb interface wi...
Wojciech Kosior
2020-09-05
add cond_jump instruction together with bench
Wojciech Kosior
2020-09-05
add jump instruction together with bench
Wojciech Kosior
2020-09-05
add mul instruction together with bench
Wojciech Kosior
2020-09-05
add div instruction together with bench
Wojciech Kosior
2020-09-05
put procedures in tclasm.tcl in some order
Wojciech Kosior
2020-09-05
add swap instruction together with bench
Wojciech Kosior
2020-09-05
add sub instruction together with bench
Wojciech Kosior
2020-09-05
add add instruction together with bench
Wojciech Kosior
2020-09-05
add tee instruction together with bench
Wojciech Kosior
2020-09-05
add Makefile target, that runs all short tests
Wojciech Kosior
2020-09-05
add tclasm multiinstructions (instructions, that possibly translate to more t...
Wojciech Kosior
2020-09-05
add load_store bench for new stack machine
Wojciech Kosior
2020-09-05
add first simple bench for new stack machine
Wojciech Kosior
2020-09-05
start another attempt for good stack machine design
Wojciech Kosior
2020-09-05
replace fixed-width constant from now-parameterized wb slave model
Wojciech Kosior
2020-09-04
add bench for parametrized instantiation of models
Wojciech Kosior
2020-09-04
fix master after parametrization
Wojciech Kosior
2020-09-04
enable parametrizable address and data widths for master model
Wojciech Kosior
2020-09-04
enable parametrizable address and data widths for slave model
Wojciech Kosior
2020-09-03
rename tclasm.tcl to tclasm_old.tcl (prepare for redesign of the stack machine)
Wojciech Kosior
2020-09-03
treat embedded RAM as read-only in test bench
Wojciech Kosior
2020-09-03
rename stack_machine to stack_machine_old (prepare for redesign of the machine)
Wojciech Kosior
2020-09-03
add the ability to synthesize the design
Wojciech Kosior
2020-09-03
make embedded memory with program code read-only (not strictly needed, but pr...
Wojciech Kosior
2020-09-03
register values immediately after reading the from embedded ram (this is requ...
Wojciech Kosior
2020-09-02
remove unnecessary complexity from preprocessor error throwing
Wojciech Kosior
2020-09-02
don't exceed 80 characters in a line
Wojciech Kosior
2020-09-02
add a VGA-based bench for entire sock
Wojciech Kosior
2020-09-02
add topmost module of the synthesizable design
Wojciech Kosior
2020-09-02
name correction: remove "wb" from "sram_wb_slave"
Wojciech Kosior
2020-09-02
add bench for embedded ram wishbone slave
Wojciech Kosior
2020-09-02
add wishbone slave with embedded bram
Wojciech Kosior
2020-09-02
add bench for wishbone sram wrapper
Wojciech Kosior
2020-09-02
add wishbone wrapper for sram
Wojciech Kosior
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