add topmost module of the synthesizable design

1 files changed, 244 insertions, 0 deletions

diff --git a/design/soc.v b/design/soc.v
new file mode 100644
index 0000000..39cdde8
--- /dev/null
+++ b/design/soc.v
@@ -0,0 +1,244 @@
+/*
+ * Topmost module in synthesis. It instantiates the intercon together with
+ * stack machine as master and 3 slaves:
+ *   slave 0 - embedded RAM (256x16) with memory initialized from file
+ *   slave 1 - SRAM
+ *   slave 2 - VGA text-mode controller
+ *
+ * The memory map from stack machine's viewpoint is as follows:
+ *   h000000 - h0001FF - embedded RAM
+ *   h000200 - h07FFFF - undefined (actually, repetitions of embedded RAM)
+ *   h080000 - h0FFFFF - SRAM
+ *   h100000 - h1009FF - VGA text memory
+ *   h100A00 - h100A01 - VGA power-on register
+ *   h100A02 - h100FFF - undefined (actually, repetitions of VGA power-on reg)
+ *   h101000 - h17FFFF - undefined (actually, repetitions of VGA memory)
+ *   h180000 - h1FFFFF - read as 0, write as don't care
+ */
+`default_nettype none
+
+`ifndef ROM_WORDS_COUNT
+ `error_ROM_WORDS_COUNT_must_be_defined
+; /* Cause syntax error */
+`endif
+
+module soc
+  #(
+    parameter FONT_FILE = "design/font.mem",
+    parameter ROM_FILE = "design/rom.mem"
+    )
+   (
+    input wire 	       clock_100mhz,
+   
+    output wire [17:0] sram_addr,
+    inout wire [15:0]  sram_io,
+
+    output wire        sram_cs_n,
+    output wire        sram_oe_n,
+    output wire        sram_we_n,
+
+    output wire        vga_hs,
+    output wire        vga_vs,
+    output wire [2:0]  vga_red,
+    output wire [2:0]  vga_green,
+    output wire [2:0]  vga_blue,
+
+    input wire 	       button1,
+    input wire 	       button2,
+
+    output wire        led1,
+    output wire        led2
+   );
+
+   wire 	       M_ACK_I;
+   wire 	       M_CLK_I;
+   wire [19:0] 	       M_ADR_O;
+   wire [15:0] 	       M_DAT_I;
+   wire [15:0] 	       M_DAT_O;
+   wire 	       M_RST_I;
+   wire 	       M_STB_O;
+   wire 	       M_CYC_O;
+   wire 	       M_WE_O;
+   wire 	       M_STALL_I;
+
+   wire 	       S0_ACK_O,   S1_ACK_O,   S2_ACK_O,   S3_ACK_O;
+   wire 	       S0_CLK_I,   S1_CLK_I,   S2_CLK_I,   S3_CLK_I;
+   wire [17:0] 	       S0_ADR_I,   S1_ADR_I,   S2_ADR_I,   S3_ADR_I;
+   wire [15:0] 	       S0_DAT_I,   S1_DAT_I,   S2_DAT_I,   S3_DAT_I;
+   wire [15:0] 	       S0_DAT_O,   S1_DAT_O,   S2_DAT_O,   S3_DAT_O;
+   wire 	       S0_RST_I,   S1_RST_I,   S2_RST_I,   S3_RST_I;
+   wire 	       S0_STB_I,   S1_STB_I,   S2_STB_I,   S3_STB_I;
+   wire 	       S0_WE_I,    S1_WE_I,    S2_WE_I,    S3_WE_I;
+   wire 	       S0_STALL_O, S1_STALL_O, S2_STALL_O, S3_STALL_O;
+
+   wire 	       CLK;
+   wire 	       RST;
+
+   /* Non-wishbone */
+   wire 	       M_finished;
+   wire 	       clock_25mhz;
+
+
+   stack_machine stack_machine
+     (
+      .ACK_I(M_ACK_I),
+      .CLK_I(M_CLK_I),
+      .ADR_O(M_ADR_O),
+      .DAT_I(M_DAT_I),
+      .DAT_O(M_DAT_O),
+      .RST_I(M_RST_I),
+      .STB_O(M_STB_O),
+      .CYC_O(M_CYC_O),
+      .WE_O(M_WE_O),
+      .STALL_I(M_STALL_I),
+
+      .finished(M_finished)
+      );
+
+   embedded_bram_slave
+     #(
+       .MEMORY_BLOCKS(1),
+       .WORDS_TO_INITIALIZE(`ROM_WORDS_COUNT),
+       .INITIAL_CONTENTS_FILE(ROM_FILE)
+       ) slave0
+       (
+	.ACK_O(S0_ACK_O),
+      	.CLK_I(S0_CLK_I),
+	.ADR_I(S0_ADR_I[7:0]),
+	.DAT_I(S0_DAT_I),
+	.DAT_O(S0_DAT_O),
+      	.RST_I(S0_RST_I),
+      	.STB_I(S0_STB_I),
+      	.WE_I(S0_WE_I),
+	.STALL_O(S0_STALL_O)
+	);
+
+   sram_slave slave1
+     (
+      .sram_addr(sram_addr),
+      .sram_io(sram_io),
+      .sram_cs_n(sram_cs_n),
+      .sram_oe_n(sram_oe_n),
+      .sram_we_n(sram_we_n),
+
+      .ACK_O(S1_ACK_O),
+      .CLK_I(S1_CLK_I),
+      .ADR_I(S1_ADR_I),
+      .DAT_I(S1_DAT_I),
+      .DAT_O(S1_DAT_O),
+      .RST_I(S1_RST_I),
+      .STB_I(S1_STB_I),
+      .WE_I(S1_WE_I),
+      .STALL_O(S1_STALL_O)
+      );
+
+   vga
+     #(
+       .FONT_FILE(FONT_FILE)
+       ) slave2
+       (
+	.ACK_O(S2_ACK_O),
+      	.CLK_I(S2_CLK_I),
+	.ADR_I(S2_ADR_I[10:0]),
+	.DAT_I(S2_DAT_I),
+	.DAT_O(S2_DAT_O),
+      	.RST_I(S2_RST_I),
+      	.STB_I(S2_STB_I),
+      	.WE_I(S2_WE_I),
+	.STALL_O(S2_STALL_O),
+
+	/* Non-wishbone */
+	.clock_25mhz(clock_25mhz),
+	.h_sync(vga_hs),
+	.v_sync(vga_vs),
+	.red(vga_red),
+	.green(vga_green),
+	.blue(vga_blue)
+	);
+
+   /* Slave 3 will be SPI controller, but for now - it's omitted */
+   assign S3_ACK_O = 1;
+   assign S3_DAT_O = 0;
+   assign S3_STALL_O = 0;
+
+   intercon intercon
+     (
+      .CLK(CLK),
+      .RST(RST),
+
+      .S0_ACK_O(S0_ACK_O),
+      .S0_CLK_I(S0_CLK_I),
+      .S0_ADR_I(S0_ADR_I),
+      .S0_DAT_I(S0_DAT_I),
+      .S0_DAT_O(S0_DAT_O),
+      .S0_RST_I(S0_RST_I),
+      .S0_STB_I(S0_STB_I),
+      .S0_WE_I(S0_WE_I),
+      .S0_STALL_O(S0_STALL_O),
+
+      .S1_ACK_O(S1_ACK_O),
+      .S1_CLK_I(S1_CLK_I),
+      .S1_ADR_I(S1_ADR_I),
+      .S1_DAT_I(S1_DAT_I),
+      .S1_DAT_O(S1_DAT_O),
+      .S1_RST_I(S1_RST_I),
+      .S1_STB_I(S1_STB_I),
+      .S1_WE_I(S1_WE_I),
+      .S1_STALL_O(S1_STALL_O),
+
+      .S2_ACK_O(S2_ACK_O),
+      .S2_CLK_I(S2_CLK_I),
+      .S2_ADR_I(S2_ADR_I),
+      .S2_DAT_I(S2_DAT_I),
+      .S2_DAT_O(S2_DAT_O),
+      .S2_RST_I(S2_RST_I),
+      .S2_STB_I(S2_STB_I),
+      .S2_WE_I(S2_WE_I),
+      .S2_STALL_O(S2_STALL_O),
+
+      .S3_ACK_O(S3_ACK_O),
+      .S3_CLK_I(S3_CLK_I),
+      .S3_ADR_I(S3_ADR_I),
+      .S3_DAT_I(S3_DAT_I),
+      .S3_DAT_O(S3_DAT_O),
+      .S3_RST_I(S3_RST_I),
+      .S3_STB_I(S3_STB_I),
+      .S3_WE_I(S3_WE_I),
+      .S3_STALL_O(S3_STALL_O),
+
+      .M_ACK_I(M_ACK_I),
+      .M_CLK_I(M_CLK_I),
+      .M_ADR_O(M_ADR_O),
+      .M_DAT_O(M_DAT_O),
+      .M_DAT_I(M_DAT_I),
+      .M_RST_I(M_RST_I),
+      .M_STB_O(M_STB_O),
+      .M_CYC_O(M_CYC_O),
+      .M_WE_O(M_WE_O),
+      .M_STALL_I(M_STALL_I)
+      );
+
+   reg [2:0] 	       clock_divider;
+   always @ (posedge clock_100mhz)
+     clock_divider <= clock_divider + 1;
+
+   assign clock_25mhz = clock_divider[1];
+   assign CLK = clock_divider[2];
+
+   reg 		       reset;
+   always @ (posedge CLK)
+     reset <= !button1;
+
+   assign RST = reset;
+
+   assign led1 = !M_finished;
+   assign led2 = !M_finished;
+
+`ifdef SIMULATION
+   /* avoid undefined values */
+   initial begin
+      clock_divider <= 0;
+      reset <= 1;
+   end
+`endif
+endmodule // soc