remove trailing whitespace

7 files changed, 10 insertions, 10 deletions

diff --git a/design/div.v b/design/div.v
index 10db627..42c7a1e 100644
--- a/design/div.v
+++ b/design/div.v
@@ -25,7 +25,7 @@ module div
    wire 		      work_remainder_sign;
    assign work_remainder = work_reg[2*WIDTH : WIDTH-1];
    assign work_remainder_sign = work_remainder[WIDTH + 1];
-			      
+
    /*
     * The following variable represents quotient using digits 1 and -1,
     * where -1 is internally represented as 0
diff --git a/design/vga.v b/design/vga.v
index b46dcbd..05a5c60 100644
--- a/design/vga.v
+++ b/design/vga.v
@@ -141,7 +141,7 @@
 	       v_counter <= 0;
 	    end else begin // if ((v_stage == V_STAGE_BB_OR_FP &&...
 	       v_counter <= v_counter + 1;
-	    end      
+	    end
 	 end // if (end_of_line)
       end else begin // if (powered_on_latched)
 	 v_stage <= V_STAGE_BB_OR_FP;
diff --git a/models/master.v b/models/master.v
index 85656f3..1793fa8 100644
--- a/models/master.v
+++ b/models/master.v
@@ -1,6 +1,6 @@
 /*
  * A wishbone slave testing module (a "mock")
- * 
+ *
  * It performs a sequence of wishbone writes, reads and waits based on contents
  * of provided .mem file. It prints error messages whenever the value it reads
  * if different from the one it expects.
@@ -42,7 +42,7 @@ module master_model
 
    parameter WORD_BITS = 8 * WORD_SIZE;
 
-   parameter 
+   parameter
      OP_READ = 0,
      OP_WRITE = 1,
      OP_WAIT = 2, /* Keep CYC_O high, but STB_O low for 1 tick */
@@ -75,7 +75,7 @@ module master_model
 
 	    j++;
 	 end
-	 
+
 	 if (operations[3*i][1:0] == OP_WRITE) begin
 	    was_read[j] <= 0;
 	    expected_data[j] <= {(8 * WORD_SIZE - 1){1'bx}};
@@ -112,7 +112,7 @@ module master_model
    assign current_op_adr
      = operations[3*operations_performed + 1][ADR_BITS - 1 : 0];
    assign current_op_data
-     = operations[3*operations_performed + 2][WORD_BITS - 1 : 0];   
+     = operations[3*operations_performed + 2][WORD_BITS - 1 : 0];
 
    assign operation_successful
      = operations_performed < OPERATIONS_COUNT &&
diff --git a/tests/div/test.v b/tests/div/test.v
index f360ebd..a98f084 100644
--- a/tests/div/test.v
+++ b/tests/div/test.v
@@ -54,7 +54,7 @@ module div_test();
 	 dividend <= 15;
 	 divisor <= 3;
 	 progress <= progress + 1;
-      end else begin	 
+      end else begin
 	 if (done) begin
 	    if (dividend / divisor === quotient && dividend % divisor === remainder) begin
 	       `DBG(("%0d/%0d computed as %0d r %0d", dividend, divisor, quotient, remainder));
diff --git a/tests/embedded_bram_slave/test.v b/tests/embedded_bram_slave/test.v
index 0ee2833..94225bd 100644
--- a/tests/embedded_bram_slave/test.v
+++ b/tests/embedded_bram_slave/test.v
@@ -68,7 +68,7 @@ module embedded_bram_test();
        .MEMORY_BLOCKS(2),
        .WORDS_TO_INITIALIZE(`ROM_WORDS_COUNT),
        .INITIAL_CONTENTS_FILE("rom.mem")
-       ) slave 
+       ) slave
        (
 	.ACK_O(S_ACK_O),
       	.CLK_I(S_CLK_I),
diff --git a/tests/self/test.v b/tests/self/test.v
index b92a63e..8eb0617 100644
--- a/tests/self/test.v
+++ b/tests/self/test.v
@@ -61,7 +61,7 @@ module self_test();
    memory_slave_model
      #(
        .SLAVE_NR(0)
-       ) slave 
+       ) slave
        (
 	.ACK_O(S_ACK_O),
       	.CLK_I(S_CLK_I),
diff --git a/tests/self_32bit_word/test.v b/tests/self_32bit_word/test.v
index 86ed660..804b4d3 100644
--- a/tests/self_32bit_word/test.v
+++ b/tests/self_32bit_word/test.v
@@ -66,7 +66,7 @@ module self_32bit_test();
        .SLAVE_NR(0),
        .WORD_SIZE(4),
        .ADR_BITS(22)
-       ) slave 
+       ) slave
        (
 	.ACK_O(S_ACK_O),
       	.CLK_I(S_CLK_I),