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| author | Wojciech Kosior <kwojtus@protonmail.com> | 2020-09-07 19:27:06 +0200 |
|---|---|---|
| committer | Wojciech Kosior <kwojtus@protonmail.com> | 2020-09-07 19:27:06 +0200 |
| commit | eb0c405f4122d416cb416b46d514278ea7dcddbf (patch) | |
| tree | f7bba6147249af69739068714188fd7390142041 | |
| parent | 328982871bb894f70eecb7868b6b6019fed76472 (diff) | |
| download | AGH-engineering-thesis-eb0c405f4122d416cb416b46d514278ea7dcddbf.tar.gz AGH-engineering-thesis-eb0c405f4122d416cb416b46d514278ea7dcddbf.zip | |
fix port directions
| -rw-r--r-- | design/slave_dispatcher.v | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/design/slave_dispatcher.v b/design/slave_dispatcher.v index 8cd0022..6377a57 100644 --- a/design/slave_dispatcher.v +++ b/design/slave_dispatcher.v @@ -39,8 +39,8 @@ module slave_dispatcher output wire S_COMBINED_ACK_O, input wire [19:0] S_COMBINED_ADR_I, - input wire [15:0] S_COMBINED_DAT_O, - output wire [15:0] S_COMBINED_DAT_I, + input wire [15:0] S_COMBINED_DAT_I, + output wire [15:0] S_COMBINED_DAT_O, input wire S_COMBINED_STB_I, input wire S_COMBINED_WE_I, output wire S_COMBINED_STALL_O |