enable slave and master models to use SEL_ signal

12 files changed, 176 insertions, 44 deletions

diff --git a/include/macroasm.vh b/include/macroasm.vh
index e6a2893..f43c809 100644
--- a/include/macroasm.vh
+++ b/include/macroasm.vh
@@ -22,7 +22,9 @@ operations:
   3 - deselect (CYC_O low for one tick)
 ))
 
-`define READ(addr, expected_data) 0 addr expected_data
-`define WRITE(addr, data)         1 addr data
-`define WAIT                      2 x x
-`define DESELECT                  3 x x
+`define READ(addr, expected_data)        0 addr expected_data FFFF
+`define READS(addr, expected_data, mask) 0 addr expected_data mask
+`define WRITE(addr, data)                1 addr data FFFF
+`define WRITES(addr, data, mask)         1 addr data mask
+`define WAIT                             2 x x x
+`define DESELECT                         3 x x x
diff --git a/models/master.v b/models/master.v
index 1793fa8..5234efe 100644
--- a/models/master.v
+++ b/models/master.v
@@ -18,7 +18,7 @@ module master_model
   #(
     parameter MASTER_NR = -1,
     parameter WORD_SIZE = 2, /* in bytes */
-    parameter GRANULARITY = 2, /* in bytes */ /* we'll use that soon */
+    parameter SEL_LINES = 1,
     parameter ADR_BITS = 20,
     parameter OPERATIONS_FILE = "master_operations.mem",
     parameter OPERATIONS_COUNT = 10
@@ -29,7 +29,7 @@ module master_model
     output wire [ADR_BITS - 1 : 0]    ADR_O,
     input wire [8*WORD_SIZE - 1 : 0]  DAT_I,
     output wire [8*WORD_SIZE - 1 : 0] DAT_O,
-    /* output wire [GRANULARITY - 1 : 0] SEL_O, */ /* we'll use that soon */
+    output wire [SEL_LINES - 1 : 0]   SEL_O,
     input wire 			      RST_I,
     output wire 		      STB_O,
     output wire 		      CYC_O,
@@ -41,6 +41,7 @@ module master_model
    );
 
    parameter WORD_BITS = 8 * WORD_SIZE;
+   parameter GRANULARITY = WORD_BITS / SEL_LINES; /* in bits */
 
    parameter
      OP_READ = 0,
@@ -52,33 +53,34 @@ module master_model
    parameter BIGGEST_WIDTH = ADR_BITS > WORD_BITS ? ADR_BITS : WORD_BITS;
    /*
     * Contents of this array determine, what this master will do.
-    * Each (3*n)th element denotes type of operation number n.
-    * (3*n+1)th element denotes address to use and (3*n+2)th element denotes
-    * data to use
+    * Each (4*n)th element denotes type of operation number n.
+    * (4*n+1)th element denotes address to use, (4*n+2)th element denotes
+    * data to use and (4*n+3)th element denotes SEL_O mask to use.
     */
-   reg [BIGGEST_WIDTH - 1 : 0] 	      operations [3*OPERATIONS_COUNT - 1 : 0];
+   reg [BIGGEST_WIDTH - 1 : 0] 	      operations [4*OPERATIONS_COUNT - 1 : 0];
 
    /* Arrays used for verifying read reaults */
    reg 				      was_read [OPERATIONS_COUNT - 1 : 0];
+   reg [SEL_LINES - 1 : 0] 	      SEL_mask [OPERATIONS_COUNT - 1 : 0];
    reg [WORD_BITS - 1 : 0] 	      expected_data [OPERATIONS_COUNT - 1 : 0];
 
    integer 			      i, j;
 
    initial begin
-      $readmemh(OPERATIONS_FILE, operations, 0, 3*OPERATIONS_COUNT - 1);
+      $readmemh(OPERATIONS_FILE, operations, 0, 4*OPERATIONS_COUNT - 1);
 
       j = 0;
       for (i = 0; i < OPERATIONS_COUNT; i++) begin
-	 if (operations[3*i][1:0] == OP_READ) begin
+	 if (operations[4*i][1:0] == OP_READ) begin
 	    was_read[j] <= 1;
-	    expected_data[j] <= operations[3*i + 2][WORD_BITS - 1 : 0];
+	    expected_data[j] <= operations[4*i + 2][WORD_BITS - 1 : 0];
+	    SEL_mask[j] <= operations[4*i + 3][SEL_LINES - 1 : 0];
 
 	    j++;
 	 end
 
-	 if (operations[3*i][1:0] == OP_WRITE) begin
+	 if (operations[4*i][1:0] == OP_WRITE) begin
 	    was_read[j] <= 0;
-	    expected_data[j] <= {(8 * WORD_SIZE - 1){1'bx}};
 
 	    j++;
 	 end
@@ -96,6 +98,7 @@ module master_model
    wire [1:0] 			      current_op_type;
    wire [ADR_BITS - 1 : 0] 	      current_op_adr;
    wire [WORD_BITS - 1 : 0] 	      current_op_data;
+   wire [SEL_LINES - 1 : 0] 	      current_op_mask;
    wire 			      operation_successful;
    wire [31:0] 			      operations_performed_next_tick;
    wire 			      acknowledgement_successful;
@@ -108,11 +111,13 @@ module master_model
    assign deselect_successful = !CYC_O;
 
    assign current_op_type
-     = operations[3*operations_performed][1:0];
+     = operations[4*operations_performed][1:0];
    assign current_op_adr
-     = operations[3*operations_performed + 1][ADR_BITS - 1 : 0];
+     = operations[4*operations_performed + 1][ADR_BITS - 1 : 0];
    assign current_op_data
-     = operations[3*operations_performed + 2][WORD_BITS - 1 : 0];
+     = operations[4*operations_performed + 2][WORD_BITS - 1 : 0];
+   assign current_op_mask
+     = operations[4*operations_performed + 3][SEL_LINES - 1 : 0];
 
    assign operation_successful
      = operations_performed < OPERATIONS_COUNT &&
@@ -135,11 +140,13 @@ module master_model
    wire [1:0] 			      next_op_type;
    wire [ADR_BITS - 1 : 0] 	      next_op_adr;
    wire [WORD_BITS - 1 : 0] 	      next_op_data;
+   wire [SEL_LINES - 1 : 0] 	      next_op_mask;
 
    assign idx_to_use = operations_performed_next_tick;
-   assign next_op_type = operations[3*idx_to_use][1:0];
-   assign next_op_adr = operations[3*idx_to_use + 1][ADR_BITS - 1 : 0];
-   assign next_op_data = operations[3*idx_to_use + 2][WORD_BITS - 1 : 0];
+   assign next_op_type = operations[4*idx_to_use][1:0];
+   assign next_op_adr = operations[4*idx_to_use + 1][ADR_BITS - 1 : 0];
+   assign next_op_data = operations[4*idx_to_use + 2][WORD_BITS - 1 : 0];
+   assign next_op_mask = operations[4*idx_to_use + 3][SEL_LINES - 1 : 0];
 
    /* Drive the outputs */
 
@@ -155,12 +162,17 @@ module master_model
    reg [WORD_BITS - 1 : 0] 	      output_data;
    assign DAT_O = output_data;
 
+   reg [SEL_LINES - 1 : 0] 	      mask;
+   assign SEL_O = mask;
+
    reg [ADR_BITS - 1 : 0] 	      addr;
    assign ADR_O = addr;
 
    reg 				      done;
    assign finished = done;
 
+   reg [WORD_BITS - 1 : 0] 	      masked_data;
+
    initial begin
       strobe <= 0;
       cycle <= 0;
@@ -221,12 +233,14 @@ module master_model
 		 cycle <= 1;
 		 strobe <= 1;
 		 write_enable <= 0;
+		 mask <= next_op_mask;
 		 addr <= next_op_adr;
 	      end
 	      OP_WRITE : begin
 		 cycle <= 1;
 		 strobe <= 1;
 		 write_enable <= 1;
+		 mask <= next_op_mask;
 		 addr <= next_op_adr;
 		 output_data <= next_op_data;
 	      end
@@ -238,16 +252,22 @@ module master_model
 		 cycle <= acknowledgements_needed > 0;
 		 strobe <= 0;
 	      end
-	    endcase // case (operation_to_perform[39:36])
+	    endcase // case (next_op_type)
 	 end // else: !if(operations_performed_next_tick == OPERATIONS_COUNT)
 
 	 if (acknowledgement_successful) begin
-	    if (expected_data[commands_acknowledged] !== DAT_I &&
+	    for (i = 0; i < WORD_BITS; i++) begin
+	       masked_data[i] = SEL_mask[commands_acknowledged][i/GRANULARITY] &
+                                DAT_I[i];
+	    end
+
+	    if (expected_data[commands_acknowledged] !== masked_data &&
 		was_read[commands_acknowledged]) begin
 	       `MSG(("Master %0d: error: read h%x instead of h%x",
-		     MASTER_NR, DAT_I, expected_data[commands_acknowledged]));
+		     MASTER_NR, masked_data,
+		     expected_data[commands_acknowledged]));
 	    end
-	 end
+	 end // if (acknowledgement_successful)
       end // else: !if(RST_I)
    end // always @ (posedge CLK_I)
 endmodule // master_model
diff --git a/models/slave.v b/models/slave.v
index f062a04..ed12a73 100644
--- a/models/slave.v
+++ b/models/slave.v
@@ -12,7 +12,7 @@ module memory_slave_model
   #(
     parameter SLAVE_NR = -1,
     parameter WORD_SIZE = 2, /* in bytes */
-    parameter GRANULARITY = 2, /* in bytes */ /* we'll use that soon */
+    parameter SEL_LINES = 1,
     parameter ADR_BITS = 18,
     /* Changing the following 3 allows us to make it function as ROM */
     parameter WRITABLE = 1,
@@ -26,21 +26,23 @@ module memory_slave_model
     input wire [ADR_BITS - 1 : 0]     ADR_I,
     input wire [8*WORD_SIZE - 1 : 0]  DAT_I,
     output wire [8*WORD_SIZE - 1 : 0] DAT_O,
-    /* input wire [GRANULARITY - 1 : 0] SEL_I, */ /* we'll use that soon */
+    input wire [SEL_LINES - 1 : 0]    SEL_I,
     input wire 			      RST_I,
     input wire 			      STB_I,
     input wire 			      WE_I,
     output wire 		      STALL_O
     );
 
+   parameter GRANULARITY = 8 * WORD_SIZE / SEL_LINES; /* in bits */
+
    /*
     * A simple memory slave should be most useful for testing purposes;
     * WARNING! The 'memory' variable might be referenced from outside the module
     * by testbench code - be careful when changing or removing it
     */
-   reg [8*WORD_SIZE - 1 : 0] 	      memory [2**ADR_BITS - 1 : 0];
+   reg [GRANULARITY - 1 : 0] 	      memory [2**ADR_BITS - 1 : 0];
 
-    /* For random stall times and acknowledge times */
+   /* For random stall times and acknowledge times */
    integer 			      seed;
 
    parameter MAX_STALL_TIME = 7;
@@ -53,6 +55,7 @@ module memory_slave_model
    reg 				      WE_I_pipeline [15:0];
    reg [ADR_BITS - 1 : 0] 	      ADR_I_pipeline [15:0];
    reg [8*WORD_SIZE - 1 : 0] 	      DAT_I_pipeline [15:0];
+   reg [SEL_LINES - 1 : 0] 	      SEL_I_pipeline [15:0];
 
    reg [3:0] 			      pipeline_oldest_element;
    reg [4:0] 			      pipeline_elements_count;
@@ -65,16 +68,19 @@ module memory_slave_model
    reg 				      WE_I_to_process;
    reg [ADR_BITS - 1 : 0] 	      ADR_I_to_process;
    reg [8*WORD_SIZE - 1 : 0] 	      DAT_I_to_process;
+   reg [SEL_LINES - 1 : 0] 	      SEL_I_to_process;
 
    always @* begin
       if (pipeline_elements_count) begin
 	 WE_I_to_process = WE_I_pipeline[pipeline_oldest_element];
 	 ADR_I_to_process = ADR_I_pipeline[pipeline_oldest_element];
 	 DAT_I_to_process = DAT_I_pipeline[pipeline_oldest_element];
+	 SEL_I_to_process = SEL_I_pipeline[pipeline_oldest_element];
       end else begin
 	 WE_I_to_process = WE_I;
 	 ADR_I_to_process = ADR_I;
 	 DAT_I_to_process = DAT_I;
+	 SEL_I_to_process = SEL_I;
       end
    end // always @ *
 
@@ -94,11 +100,27 @@ module memory_slave_model
 				 command_available_for_acknowledging;
 
 
+   integer                   i; /* loop counter */
+   reg [8*WORD_SIZE - 1 : 0] masked_out_data;
+
+   always @ (SEL_I_to_process or WE_I_to_process or ADR_I_to_process) begin
+      for (i = SEL_LINES - 1; i >= 0; i--) begin
+	 if (SEL_LINES > 1) begin
+	    masked_out_data[8*WORD_SIZE - 1 : GRANULARITY]
+	      = masked_out_data[8*WORD_SIZE - GRANULARITY - 1 : 0];
+	 end
+
+	 masked_out_data[GRANULARITY - 1 : 0]
+	   = SEL_I_to_process[i] ?
+	     memory[ADR_I_to_process + i] : {GRANULARITY{1'bx}};
+      end
+   end // always @ (SEL_I_to_process or WE_I_to_process or ADR_I_to_process)
+
    /* Finally, drive the outputs */
 
    /* only drive data outputs for read commands */
    assign DAT_O = (command_acknowledged && !WE_I_to_process) ?
-		  memory[ADR_I_to_process] : {(8 * WORD_SIZE - 1){1'bx}};
+		  masked_out_data : {(8 * WORD_SIZE - 1){1'bx}};
 
    assign STALL_O = !can_accept;
 
@@ -115,6 +137,9 @@ module memory_slave_model
 	$readmemb(INITIAL_CONTENTS_FILE, memory, 0, WORDS_TO_INITIALIZE - 1);
    end
 
+   integer                   k; /* loop counter */
+   reg [8*WORD_SIZE - 1 : 0] masked_in_data;
+
    always @ (posedge CLK_I) begin
       if (RST_I) begin
 	 pipeline_oldest_element <= 0;
@@ -125,6 +150,7 @@ module memory_slave_model
 	    WE_I_pipeline[pipeline_index_to_insert] <= WE_I;
 	    ADR_I_pipeline[pipeline_index_to_insert] <= ADR_I;
 	    DAT_I_pipeline[pipeline_index_to_insert] <= DAT_I;
+	    SEL_I_pipeline[pipeline_index_to_insert] <= SEL_I;
 	 end else begin
 	    if (stall_time_left)
 	      stall_time_left <= stall_time_left - 1;
@@ -135,18 +161,36 @@ module memory_slave_model
 	    pipeline_oldest_element <= pipeline_oldest_element + 1;
 
 	    if (WE_I_to_process) begin /* Write command */
+	       masked_in_data = DAT_I_to_process;
+
+	       for (k = 0; k < SEL_LINES; k++) begin
+		  if (SEL_I_to_process[k]) begin
+		     if (WRITABLE) begin
+			memory[ADR_I_to_process + k]
+			  <= masked_in_data[GRANULARITY - 1 : 0];
+		     end
+		  end else begin
+		     masked_in_data[GRANULARITY - 1 : 0] = {GRANULARITY{1'bx}};
+		  end
+
+		  if (SEL_LINES > 1) begin
+		     masked_in_data
+		       = {masked_in_data[GRANULARITY - 1 : 0],
+			  masked_in_data[8*WORD_SIZE - 1 : GRANULARITY]};
+		  end
+	       end // for (k = 0; k < SEL_LINES; k++)
+
 	       if (WRITABLE) begin
-		  memory[ADR_I_to_process] <= DAT_I_to_process;
-		  `DBG(("Slave %0d: write of h%x at h%x", SLAVE_NR,
-			DAT_I_to_process, ADR_I_to_process));
+		  `DBG(("Slave %0d: write of h%x (%b) at h%x", SLAVE_NR,
+			masked_in_data, SEL_I_to_process, ADR_I_to_process));
 	       end else begin
-		  `DBG(({"Slave %0d: error: write of h%x at h%x ",
+		  `DBG(({"Slave %0d: error: write of h%x (%b) at h%x ",
 			 "(read-only) memory"}, SLAVE_NR,
-			DAT_I_to_process, ADR_I_to_process));
+			DAT_I_to_process, SEL_I_to_process, ADR_I_to_process));
 	       end
 	    end else begin /* Read command */
-	       `DBG(("Slave %0d: read of h%x at h%x", SLAVE_NR,
-		     DAT_O, ADR_I_to_process));
+	       `DBG(("Slave %0d: read of h%x (%b) at h%x", SLAVE_NR,
+		     DAT_O, SEL_I_to_process, ADR_I_to_process));
 	    end
 	 end else if (command_available_for_acknowledging) begin
 	    acknowledge_time_left <= acknowledge_time_left - 1;
diff --git a/tests/embedded_bram_slave/test.v b/tests/embedded_bram_slave/test.v
index 94225bd..3671992 100644
--- a/tests/embedded_bram_slave/test.v
+++ b/tests/embedded_bram_slave/test.v
@@ -23,6 +23,7 @@ module embedded_bram_test();
    wire [19:0] M_ADR_O;
    wire [15:0] M_DAT_I;
    wire [15:0] M_DAT_O;
+   wire        M_SEL_O; /* Ignored, assumed always high */
    wire        M_RST_I;
    wire        M_STB_O;
    wire        M_CYC_O;
@@ -54,6 +55,7 @@ module embedded_bram_test();
 	.ADR_O(M_ADR_O),
 	.DAT_I(M_DAT_I),
 	.DAT_O(M_DAT_O),
+	.SEL_O(M_SEL_O),
  	.RST_I(M_RST_I),
 	.STB_O(M_STB_O),
 	.CYC_O(M_CYC_O),
diff --git a/tests/intercon/test.v b/tests/intercon/test.v
index 313f4c6..f2102a6 100644
--- a/tests/intercon/test.v
+++ b/tests/intercon/test.v
@@ -25,6 +25,7 @@ module intercon_test();
    wire [19:0] M0_ADR_O,   M1_ADR_O;
    wire [15:0] M0_DAT_I,   M1_DAT_I;
    wire [15:0] M0_DAT_O,   M1_DAT_O;
+   wire        M0_SEL_O,   M1_SEL_O; /* Ignored, assumed always high */
    wire        M0_STB_O,   M1_STB_O;
    wire        M0_CYC_O,   M1_CYC_O;
    wire        M0_WE_O,    M1_WE_O;
@@ -35,6 +36,7 @@ module intercon_test();
    wire [17:0] S0_ADR_I,   S1_ADR_I,   S2_ADR_I,   S3_ADR_I;
    wire [15:0] S0_DAT_I,   S1_DAT_I,   S2_DAT_I,   S3_DAT_I;
    wire [15:0] S0_DAT_O,   S1_DAT_O,   S2_DAT_O,   S3_DAT_O;
+   wire        S0_SEL_I,   S1_SEL_I,   S2_SEL_I,   S3_SEL_I; /* Always high */
    wire        S0_RST_I,   S1_RST_I,   S2_RST_I,   S3_RST_I;
    wire        S0_STB_I,   S1_STB_I,   S2_STB_I,   S3_STB_I;
    wire        S0_WE_I,    S1_WE_I,    S2_WE_I,    S3_WE_I;
@@ -58,6 +60,7 @@ module intercon_test();
 	.ADR_O(M0_ADR_O),
 	.DAT_I(M0_DAT_I),
 	.DAT_O(M0_DAT_O),
+	.SEL_O(M0_SEL_O),
  	.RST_I(RST),
 	.STB_O(M0_STB_O),
 	.CYC_O(M0_CYC_O),
@@ -81,6 +84,7 @@ module intercon_test();
 	.ADR_O(M1_ADR_O),
 	.DAT_I(M1_DAT_I),
 	.DAT_O(M1_DAT_O),
+	.SEL_O(M1_SEL_O),
  	.RST_I(RST),
 	.STB_O(M1_STB_O),
 	.CYC_O(M1_CYC_O),
@@ -100,6 +104,7 @@ module intercon_test();
 	.ADR_I(S0_ADR_I),
 	.DAT_I(S0_DAT_I),
 	.DAT_O(S0_DAT_O),
+	.SEL_I(S0_SEL_I),
       	.RST_I(RST),
       	.STB_I(S0_STB_I),
       	.WE_I(S0_WE_I),
@@ -116,6 +121,7 @@ module intercon_test();
 	.ADR_I(S1_ADR_I),
 	.DAT_I(S1_DAT_I),
 	.DAT_O(S1_DAT_O),
+	.SEL_I(S1_SEL_I),
       	.RST_I(RST),
       	.STB_I(S1_STB_I),
       	.WE_I(S1_WE_I),
@@ -132,6 +138,7 @@ module intercon_test();
 	.ADR_I(S2_ADR_I),
 	.DAT_I(S2_DAT_I),
 	.DAT_O(S2_DAT_O),
+	.SEL_I(S2_SEL_I),
       	.RST_I(RST),
       	.STB_I(S2_STB_I),
       	.WE_I(S2_WE_I),
@@ -148,6 +155,7 @@ module intercon_test();
 	.ADR_I(S3_ADR_I),
 	.DAT_I(S3_DAT_I),
 	.DAT_O(S3_DAT_O),
+	.SEL_I(S3_SEL_I),
       	.RST_I(RST),
       	.STB_I(S3_STB_I),
       	.WE_I(S3_WE_I),
@@ -210,6 +218,11 @@ module intercon_test();
       .M1_STALL_I(M1_STALL_I)
       );
 
+   assign S0_SEL_I = 1;
+   assign S1_SEL_I = 1;
+   assign S2_SEL_I = 1;
+   assign S3_SEL_I = 1;
+
    integer     i;
 
    initial begin
diff --git a/tests/interface_wrapper/test.v b/tests/interface_wrapper/test.v
index cbd3d88..4031f35 100644
--- a/tests/interface_wrapper/test.v
+++ b/tests/interface_wrapper/test.v
@@ -22,7 +22,7 @@ module interface_wrapper_test();
    wire [20:0] M_RAW_ADR_O;
    wire [31:0] M_RAW_DAT_I;
    wire [31:0] M_RAW_DAT_O;
-   wire [3:0]  M_RAW_SEL_O; /* Not used yet, always 4'hF */
+   wire [3:0]  M_RAW_SEL_O; /* This is being worked on */
    wire        M_RAW_STB_O;
    wire        M_RAW_CYC_O;
    wire        M_RAW_WE_O;
@@ -42,6 +42,7 @@ module interface_wrapper_test();
    wire [19:0] S_ADR_I;
    wire [15:0] S_DAT_I;
    wire [15:0] S_DAT_O;
+   wire        S_SEL_I; /* Always high */
    wire        S_RST_I;
    wire        S_STB_I;
    wire        S_WE_I;
@@ -54,6 +55,7 @@ module interface_wrapper_test();
      #(
        .MASTER_NR(0),
        .WORD_SIZE(4),
+       .SEL_LINES(4),
        .ADR_BITS(21),
        .OPERATIONS_FILE("operations.mem"),
        .OPERATIONS_COUNT(`MASTER_OPERATIONS_COUNT)
@@ -64,6 +66,7 @@ module interface_wrapper_test();
 	.ADR_O(M_RAW_ADR_O),
 	.DAT_I(M_RAW_DAT_I),
 	.DAT_O(M_RAW_DAT_O),
+	.SEL_O(M_RAW_SEL_O),
  	.RST_I(M_RST_I),
 	.STB_O(M_RAW_STB_O),
 	.CYC_O(M_RAW_CYC_O),
@@ -85,6 +88,7 @@ module interface_wrapper_test();
 	.ADR_I(S_ADR_I),
 	.DAT_I(S_DAT_I),
 	.DAT_O(S_DAT_O),
+	.SEL_I(S_SEL_I),
       	.RST_I(S_RST_I),
       	.STB_I(S_STB_I),
       	.WE_I(S_WE_I),
@@ -127,11 +131,10 @@ interface_wrapper wrapper
    assign M_WRAPPED_DAT_I = S_DAT_O;
    assign M_WRAPPED_STALL_I = S_STALL_O;
 
-   assign M_RAW_SEL_O = 4'hF;
-
    assign S_CLK_I = CLK;
    assign S_ADR_I = M_WRAPPED_ADR_O;
    assign S_DAT_I = M_WRAPPED_DAT_O;
+   assign S_SEL_I = 1;
    assign S_RST_I = RST;
    assign S_STB_I = M_WRAPPED_STB_O && M_WRAPPED_CYC_O;
    assign S_WE_I = M_WRAPPED_WE_O;
diff --git a/tests/master_arbiter/test.v b/tests/master_arbiter/test.v
index bcf90b8..58e3add 100644
--- a/tests/master_arbiter/test.v
+++ b/tests/master_arbiter/test.v
@@ -22,6 +22,7 @@ module master_arbiter_test();
    wire [19:0] M0_ADR_O;
    wire [15:0] M0_DAT_I;
    wire [15:0] M0_DAT_O;
+   wire        M0_SEL_O; /* Ignored, assumed always high */
    wire        M0_STB_O;
    wire        M0_CYC_O;
    wire        M0_WE_O;
@@ -31,6 +32,7 @@ module master_arbiter_test();
    wire [19:0] M1_ADR_O;
    wire [15:0] M1_DAT_I;
    wire [15:0] M1_DAT_O;
+   wire        M1_SEL_O; /* Ignored, assumed always high */
    wire        M1_STB_O;
    wire        M1_CYC_O;
    wire        M1_WE_O;
@@ -40,6 +42,7 @@ module master_arbiter_test();
    wire [19:0] S_ADR_I;
    wire [15:0] S_DAT_I;
    wire [15:0] S_DAT_O;
+   wire        S_SEL_I; /* Always high */
    wire        S_STB_I;
    wire        S_WE_I;
    wire        S_STALL_O;
@@ -76,6 +79,7 @@ module master_arbiter_test();
 	.ADR_O(M0_ADR_O),
 	.DAT_I(M0_DAT_I),
 	.DAT_O(M0_DAT_O),
+	.SEL_O(M0_SEL_O),
  	.RST_I(RST),
 	.STB_O(M0_STB_O),
 	.CYC_O(M0_CYC_O),
@@ -99,6 +103,7 @@ module master_arbiter_test();
 	.ADR_O(M1_ADR_O),
 	.DAT_I(M1_DAT_I),
 	.DAT_O(M1_DAT_O),
+	.SEL_O(M1_SEL_O),
  	.RST_I(RST),
 	.STB_O(M1_STB_O),
 	.CYC_O(M1_CYC_O),
@@ -120,6 +125,7 @@ module master_arbiter_test();
 	.ADR_I(S_ADR_I),
 	.DAT_I(S_DAT_I),
 	.DAT_O(S_DAT_O),
+	.SEL_I(S_SEL_I),
       	.RST_I(RST),
       	.STB_I(S_STB_I),
       	.WE_I(S_WE_I),
@@ -165,6 +171,7 @@ module master_arbiter_test();
 
    assign S_ADR_I = M_COMBINED_ADR_O[19:0];
    assign S_DAT_I = M_COMBINED_DAT_O;
+   assign S_SEL_I = 1;
    assign S_STB_I = M_COMBINED_STB_O && M_COMBINED_CYC_O;
    assign S_WE_I = M_COMBINED_WE_O;
 
diff --git a/tests/self/test.v b/tests/self/test.v
index 8eb0617..323dba2 100644
--- a/tests/self/test.v
+++ b/tests/self/test.v
@@ -18,6 +18,7 @@ module self_test();
    wire [19:0] M_ADR_O;
    wire [15:0] M_DAT_I;
    wire [15:0] M_DAT_O;
+   wire        M_SEL_O; /* Always high in this test */
    wire        M_RST_I;
    wire        M_STB_O;
    wire        M_CYC_O;
@@ -29,6 +30,7 @@ module self_test();
    wire [17:0] S_ADR_I;
    wire [15:0] S_DAT_I;
    wire [15:0] S_DAT_O;
+   wire        S_SEL_I; /* Always high in this test */
    wire        S_RST_I;
    wire        S_STB_I;
    wire        S_WE_I;
@@ -49,6 +51,7 @@ module self_test();
 	.ADR_O(M_ADR_O),
 	.DAT_I(M_DAT_I),
 	.DAT_O(M_DAT_O),
+	.SEL_O(M_SEL_O),
  	.RST_I(M_RST_I),
 	.STB_O(M_STB_O),
 	.CYC_O(M_CYC_O),
@@ -68,6 +71,7 @@ module self_test();
 	.ADR_I(S_ADR_I),
 	.DAT_I(S_DAT_I),
 	.DAT_O(S_DAT_O),
+	.SEL_I(S_SEL_I),
       	.RST_I(S_RST_I),
       	.STB_I(S_STB_I),
       	.WE_I(S_WE_I),
@@ -86,6 +90,7 @@ module self_test();
    assign S_CLK_I = CLK;
    assign S_ADR_I = M_ADR_O[17:0]; /* Ignore 2 topmost bits */
    assign S_DAT_I = M_DAT_O;
+   assign S_SEL_I = M_SEL_O;
    assign S_RST_I = RST;
    assign S_STB_I = M_STB_O && M_CYC_O;
    assign S_WE_I = M_WE_O;
diff --git a/tests/self_32bit_word/test.v b/tests/self_32bit_word/test.v
index 804b4d3..871fe0c 100644
--- a/tests/self_32bit_word/test.v
+++ b/tests/self_32bit_word/test.v
@@ -19,6 +19,7 @@ module self_32bit_test();
    wire [21:0] M_ADR_O;
    wire [31:0] M_DAT_I;
    wire [31:0] M_DAT_O;
+   wire [3:0]  M_SEL_O;
    wire        M_RST_I;
    wire        M_STB_O;
    wire        M_CYC_O;
@@ -30,6 +31,7 @@ module self_32bit_test();
    wire [21:0] S_ADR_I;
    wire [31:0] S_DAT_I;
    wire [31:0] S_DAT_O;
+   wire [3:0]  S_SEL_I;
    wire        S_RST_I;
    wire        S_STB_I;
    wire        S_WE_I;
@@ -42,6 +44,7 @@ module self_32bit_test();
      #(
        .MASTER_NR(0),
        .WORD_SIZE(4),
+       .SEL_LINES(4),
        .ADR_BITS(22),
        .OPERATIONS_FILE("operations.mem"),
        .OPERATIONS_COUNT(`MASTER_OPERATIONS_COUNT)
@@ -52,6 +55,7 @@ module self_32bit_test();
 	.ADR_O(M_ADR_O),
 	.DAT_I(M_DAT_I),
 	.DAT_O(M_DAT_O),
+	.SEL_O(M_SEL_O),
  	.RST_I(M_RST_I),
 	.STB_O(M_STB_O),
 	.CYC_O(M_CYC_O),
@@ -65,6 +69,7 @@ module self_32bit_test();
      #(
        .SLAVE_NR(0),
        .WORD_SIZE(4),
+       .SEL_LINES(4),
        .ADR_BITS(22)
        ) slave
        (
@@ -73,6 +78,7 @@ module self_32bit_test();
 	.ADR_I(S_ADR_I),
 	.DAT_I(S_DAT_I),
 	.DAT_O(S_DAT_O),
+	.SEL_I(S_SEL_I),
       	.RST_I(S_RST_I),
       	.STB_I(S_STB_I),
       	.WE_I(S_WE_I),
@@ -91,6 +97,7 @@ module self_32bit_test();
    assign S_CLK_I = CLK;
    assign S_ADR_I = M_ADR_O;
    assign S_DAT_I = M_DAT_O;
+   assign S_SEL_I = M_SEL_O;
    assign S_RST_I = RST;
    assign S_STB_I = M_STB_O && M_CYC_O;
    assign S_WE_I = M_WE_O;
diff --git a/tests/slave_dispatcher/test.v b/tests/slave_dispatcher/test.v
index d29b05c..49c03ef 100644
--- a/tests/slave_dispatcher/test.v
+++ b/tests/slave_dispatcher/test.v
@@ -20,6 +20,7 @@ module slave_dispatcher_test();
    wire [19:0] M_ADR_O;
    wire [15:0] M_DAT_I;
    wire [15:0] M_DAT_O;
+   wire        M_SEL_O; /* Ignored, assumed always high */
    wire        M_STB_O;
    wire        M_CYC_O;
    wire        M_WE_O;
@@ -30,6 +31,7 @@ module slave_dispatcher_test();
    wire [17:0] S0_ADR_I,   S1_ADR_I,   S2_ADR_I,   S3_ADR_I;
    wire [15:0] S0_DAT_I,   S1_DAT_I,   S2_DAT_I,   S3_DAT_I;
    wire [15:0] S0_DAT_O,   S1_DAT_O,   S2_DAT_O,   S3_DAT_O;
+   wire        S0_SEL_I,   S1_SEL_I,   S2_SEL_I,   S3_SEL_I; /* Always high */
    wire        S0_RST_I,   S1_RST_I,   S2_RST_I,   S3_RST_I;
    wire        S0_STB_I,   S1_STB_I,   S2_STB_I,   S3_STB_I;
    wire        S0_WE_I,    S1_WE_I,    S2_WE_I,    S3_WE_I;
@@ -57,6 +59,7 @@ module slave_dispatcher_test();
 	.ADR_O(M_ADR_O),
 	.DAT_I(M_DAT_I),
 	.DAT_O(M_DAT_O),
+	.SEL_O(M_SEL_O),
  	.RST_I(RST),
 	.STB_O(M_STB_O),
 	.CYC_O(M_CYC_O),
@@ -76,6 +79,7 @@ module slave_dispatcher_test();
 	.ADR_I(S0_ADR_I),
 	.DAT_I(S0_DAT_I),
 	.DAT_O(S0_DAT_O),
+	.SEL_I(S0_SEL_I),
       	.RST_I(RST),
       	.STB_I(S0_STB_I),
       	.WE_I(S0_WE_I),
@@ -92,6 +96,7 @@ module slave_dispatcher_test();
 	.ADR_I(S1_ADR_I),
 	.DAT_I(S1_DAT_I),
 	.DAT_O(S1_DAT_O),
+	.SEL_I(S1_SEL_I),
       	.RST_I(RST),
       	.STB_I(S1_STB_I),
       	.WE_I(S1_WE_I),
@@ -108,6 +113,7 @@ module slave_dispatcher_test();
 	.ADR_I(S2_ADR_I),
 	.DAT_I(S2_DAT_I),
 	.DAT_O(S2_DAT_O),
+	.SEL_I(S2_SEL_I),
       	.RST_I(RST),
       	.STB_I(S2_STB_I),
       	.WE_I(S2_WE_I),
@@ -124,6 +130,7 @@ module slave_dispatcher_test();
 	.ADR_I(S3_ADR_I),
 	.DAT_I(S3_DAT_I),
 	.DAT_O(S3_DAT_O),
+	.SEL_I(S3_SEL_I),
       	.RST_I(RST),
       	.STB_I(S3_STB_I),
       	.WE_I(S3_WE_I),
@@ -185,6 +192,11 @@ module slave_dispatcher_test();
    assign S_COMBINED_STB_I = M_STB_O && M_CYC_O;
    assign S_COMBINED_WE_I = M_WE_O;
 
+   assign S0_SEL_I = 1;
+   assign S1_SEL_I = 1;
+   assign S2_SEL_I = 1;
+   assign S3_SEL_I = 1;
+
    integer     i;
 
    initial begin
diff --git a/tests/stack_machine_store/test.v b/tests/stack_machine_store/test.v
index 08230a3..98ea2dc 100644
--- a/tests/stack_machine_store/test.v
+++ b/tests/stack_machine_store/test.v
@@ -36,7 +36,7 @@ module stack_machine_test();
    wire [20:0] MD_ADR_O;
    wire [31:0] MD_DAT_I;
    wire [31:0] MD_DAT_O;
-   wire [3:0]  MD_SEL_O; /* Ignored for now */
+   wire [3:0]  MD_SEL_O;
    wire        MD_STB_O;
    wire        MD_CYC_O;
    wire        MD_WE_O;
@@ -48,6 +48,7 @@ module stack_machine_test();
    wire [19:0] SI_ADR_I;
    wire [15:0] SI_DAT_I;
    wire [15:0] SI_DAT_O;
+   wire        SI_SEL_I;
    wire        SI_RST_I;
    wire        SI_STB_I;
    wire        SI_WE_I;
@@ -58,6 +59,7 @@ module stack_machine_test();
    wire [20:0] SD_ADR_I;
    wire [31:0] SD_DAT_I;
    wire [31:0] SD_DAT_O;
+   wire [3:0]  SD_SEL_I;
    wire        SD_RST_I;
    wire        SD_STB_I;
    wire        SD_WE_I;
@@ -111,6 +113,7 @@ module stack_machine_test();
 	.ADR_I(SI_ADR_I),
 	.DAT_I(SI_DAT_I),
 	.DAT_O(SI_DAT_O),
+	.SEL_I(SI_SEL_I),
       	.RST_I(SI_RST_I),
       	.STB_I(SI_STB_I),
       	.WE_I(SI_WE_I),
@@ -121,6 +124,7 @@ module stack_machine_test();
      #(
        .SLAVE_NR(1),
        .WORD_SIZE(4),
+       .SEL_LINES(4),
        .ADR_BITS(21),
        .WRITABLE(1),
        .WORDS_TO_INITIALIZE(`INSTRUCTIONS_COUNT),
@@ -132,6 +136,7 @@ module stack_machine_test();
 	.ADR_I(SD_ADR_I),
 	.DAT_I(SD_DAT_I),
 	.DAT_O(SD_DAT_O),
+	.SEL_I(SD_SEL_I),
       	.RST_I(SD_RST_I),
       	.STB_I(SD_STB_I),
       	.WE_I(SD_WE_I),
@@ -155,6 +160,7 @@ module stack_machine_test();
    assign SI_CLK_I = CLK;
    assign SI_ADR_I = MI_ADR_O;
    assign SI_DAT_I = MI_DAT_O;
+   assign SI_SEL_I = 1;
    assign SI_RST_I = RST;
    assign SI_STB_I = MI_STB_O && MI_CYC_O;
    assign SI_WE_I = MI_WE_O;
@@ -162,6 +168,7 @@ module stack_machine_test();
    assign SD_CLK_I = CLK;
    assign SD_ADR_I = MD_ADR_O;
    assign SD_DAT_I = MD_DAT_O;
+   assign SD_SEL_I = MD_SEL_O;
    assign SD_RST_I = RST;
    assign SD_STB_I = MD_STB_O && MD_CYC_O;
    assign SD_WE_I = MD_WE_O;
@@ -169,6 +176,7 @@ module stack_machine_test();
    integer     i, j;
    reg [21:0]  address;
    reg [31:0]  expected_value;
+   reg [31:0]  found_value;
 
    reg [31:0]  words_to_verify[`WORDS_TO_VERIFY_COUNT * 2 - 1 : 0];
 
@@ -189,12 +197,15 @@ module stack_machine_test();
 		      0, `WORDS_TO_VERIFY_COUNT * 2 - 1);
 
 	    for (j = 0; j < `WORDS_TO_VERIFY_COUNT; j++) begin
-	       /* Keep in mind we haven't implemented byte-grained access yet */
 	       address = words_to_verify[2 * j][21:0];
+	       found_value = {slave_D.memory[address + 3],
+                              slave_D.memory[address + 2],
+                              slave_D.memory[address + 1],
+                              slave_D.memory[address]};
 	       expected_value = words_to_verify[2 * j + 1];
-	       if (slave_D.memory[address] !== expected_value) begin
+	       if (found_value !== expected_value) begin
 		  `MSG(("error: expected h%x at h%x, but got h%x",
-			expected_value, address, slave_D.memory[address]));
+			expected_value, address, found_value));
 	       end
 	    end
 
diff --git a/tests/wrapped_stack_machine_cond_jump/test.v b/tests/wrapped_stack_machine_cond_jump/test.v
index 4dff60c..7845045 100644
--- a/tests/wrapped_stack_machine_cond_jump/test.v
+++ b/tests/wrapped_stack_machine_cond_jump/test.v
@@ -44,6 +44,7 @@ module wrapped_stack_machine_test();
    wire [19:0] SI_ADR_I;
    wire [15:0] SI_DAT_I;
    wire [15:0] SI_DAT_O;
+   wire        SI_SEL_I;
    wire        SI_STB_I;
    wire        SI_WE_I;
    wire        SI_STALL_O;
@@ -52,6 +53,7 @@ module wrapped_stack_machine_test();
    wire [19:0] SD_ADR_I;
    wire [15:0] SD_DAT_I;
    wire [15:0] SD_DAT_O;
+   wire        SD_SEL_I;
    wire        SD_STB_I;
    wire        SD_WE_I;
    wire        SD_STALL_O;
@@ -102,6 +104,7 @@ module wrapped_stack_machine_test();
 	.ADR_I(SI_ADR_I),
 	.DAT_I(SI_DAT_I),
 	.DAT_O(SI_DAT_O),
+	.SEL_I(SI_SEL_I),
       	.RST_I(RST),
       	.STB_I(SI_STB_I),
       	.WE_I(SI_WE_I),
@@ -121,6 +124,7 @@ module wrapped_stack_machine_test();
 	.ADR_I(SD_ADR_I),
 	.DAT_I(SD_DAT_I),
 	.DAT_O(SD_DAT_O),
+	.SEL_I(SD_SEL_I),
       	.RST_I(RST),
       	.STB_I(SD_STB_I),
       	.WE_I(SD_WE_I),
@@ -137,11 +141,13 @@ module wrapped_stack_machine_test();
 
    assign SI_ADR_I = MI_ADR_O;
    assign SI_DAT_I = MI_DAT_O;
+   assign SI_SEL_I = 1;
    assign SI_STB_I = MI_STB_O && MI_CYC_O;
    assign SI_WE_I = MI_WE_O;
 
    assign SD_ADR_I = MD_ADR_O;
    assign SD_DAT_I = MD_DAT_O;
+   assign SD_SEL_I = 1;
    assign SD_STB_I = MD_STB_O && MD_CYC_O;
    assign SD_WE_I = MD_WE_O;