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| author | Wojciech Kosior <kwojtus@protonmail.com> | 2020-09-08 17:42:44 +0200 |
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| committer | Wojciech Kosior <kwojtus@protonmail.com> | 2020-09-08 17:42:44 +0200 |
| commit | dfcd082cd2290fb39d8cb322f2ab70f0e8752ef7 (patch) | |
| tree | f8a2d4501bfb97090e94ffb9520cce39234aceb6 | |
| parent | cbc2686373a5fe81b6b28f845edc323d4cae56e5 (diff) | |
| download | AGH-engineering-thesis-dfcd082cd2290fb39d8cb322f2ab70f0e8752ef7.tar.gz AGH-engineering-thesis-dfcd082cd2290fb39d8cb322f2ab70f0e8752ef7.zip | |
Update README
| -rw-r--r-- | README.txt | 22 |
1 files changed, 15 insertions, 7 deletions
@@ -29,8 +29,7 @@ WebAsm binary format was not designed for direct execution, so I'm instead creating a minimal stack machine, that would allow almost 1:1 translation of Wasm code to it's own instruction format. I still think it's possible to make a CPU, that would execute Wasm directly - it's just matter of a bit more -effort. Right now I'm not describing the instruction format of my stack -machine, because it is likely to change. +effort. The stack machine is and will be limited. That's why some more complex Wasm instructions (e.g. 64-bit operations, maybe float operations) have to be @@ -55,13 +54,20 @@ it pseudo-assembly. Before embracing tcl, I needed a way to express memory reads and writes for some test benches and created a simple macroassembly (include/macroasm.vh). I probably should have used tcl from the beginning... -Everything is done through a (rather complex) Makefile. +Everything is done through some (quite sophisticated) Makefiles. ## Project structure - Makefile - needs no explaination... - - design/ - Verilog sources, that will get synthesized for FPGA + - Makefile.config - included by Makefile and Makefile.test, defines variables, + makes it easy to, e.g., change the compiler command + - Makefile.util - also included by Makefile and Makefile.test - defines things, + that didn't semantically fit into Makefile.config + - design/ - Verilog sources, that will get synthesized for FPGA (+some other + files like initial memory contents) - models/ - Verilog modules used in testing - - tests/ - benches, each in its own subdirectory + - tests/ - benches, each in its own subdirectory, with a Makefile including + Makefile.test + - tclasm.tcl - implementation of simple assembly in terms of tcl commands - include/ - Verilog header files for inclusion - tools/ - small C programs - COPYING - 0BSD license @@ -82,8 +88,10 @@ then write tests for it. I'm now determined to use Wishbone, because I believe it helps me keep the design clean. My stack machine is currently able to do some operations like memory accesses, -addition and unsigned division, but it's not yet ready to have Wasm translated -for it. I'm also thinking about radically changing its design... +addition and unsigned division, jumps, but it's not yet ready to have most of +Wasm translated to it. At the beginning of September I changed the design and +instruction format and rewrote the stack machine. The current one can be +considered my third approach :p ### Thoughts It's indeed an interesting project, but from practical point of view - it's |