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author | Wojciech Kosior <kwojtus@protonmail.com> | 2020-09-04 17:22:40 +0200 |
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committer | Wojciech Kosior <kwojtus@protonmail.com> | 2020-09-04 17:22:40 +0200 |
commit | e724f3543ea145386ca02999346bc784ee6e448f (patch) | |
tree | 91a0461b3da414144a7097932b784d3fdae6b8e7 | |
parent | 8651fe2b0f78569d4fc1c182833a08d6e463ebe6 (diff) | |
download | AGH-engineering-thesis-e724f3543ea145386ca02999346bc784ee6e448f.tar.gz AGH-engineering-thesis-e724f3543ea145386ca02999346bc784ee6e448f.zip |
fix master after parametrization
-rw-r--r-- | models/master.v | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/models/master.v b/models/master.v index 5c8bacf..85656f3 100644 --- a/models/master.v +++ b/models/master.v @@ -143,22 +143,22 @@ module master_model /* Drive the outputs */ - reg strobe; + reg strobe; assign STB_O = strobe; - reg cycle; + reg cycle; assign CYC_O = cycle; - reg write_enable; + reg write_enable; assign WE_O = write_enable; - reg [15:0] output_data; + reg [WORD_BITS - 1 : 0] output_data; assign DAT_O = output_data; - reg [19:0] addr; + reg [ADR_BITS - 1 : 0] addr; assign ADR_O = addr; - reg done; + reg done; assign finished = done; initial begin |