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| author | Wojciech Kosior <kwojtus@protonmail.com> | 2020-09-02 20:36:27 +0200 |
|---|---|---|
| committer | Wojciech Kosior <kwojtus@protonmail.com> | 2020-09-02 20:36:27 +0200 |
| commit | fe733d971b4eeef8f5decfb762de01e57f977734 (patch) | |
| tree | 1d5754f1bf5ca960f9e53dc2c9e78d044282ddd3 | |
| parent | 88e9df29ed884b1ef0f5795755d8259b00727f55 (diff) | |
| download | AGH-engineering-thesis-fe733d971b4eeef8f5decfb762de01e57f977734.tar.gz AGH-engineering-thesis-fe733d971b4eeef8f5decfb762de01e57f977734.zip | |
remove unnecessary complexity from preprocessor error throwing
| -rw-r--r-- | models/master.v | 4 | ||||
| -rw-r--r-- | models/slave.v | 4 |
2 files changed, 2 insertions, 6 deletions
diff --git a/models/master.v b/models/master.v index b728bda..0e128ec 100644 --- a/models/master.v +++ b/models/master.v @@ -6,7 +6,7 @@ `ifndef SIMULATION `error_SIMULATION_not_defined ; /* Cause syntax error */ -`else +`endif module master_model #( @@ -219,5 +219,3 @@ module master_model end // else: !if(RST_I) end // always @ (posedge CLK_I) endmodule // master_model - -`endif // !`ifndef SIMULATION diff --git a/models/slave.v b/models/slave.v index bae3485..9c58ffd 100644 --- a/models/slave.v +++ b/models/slave.v @@ -6,7 +6,7 @@ `ifndef SIMULATION `error_SIMULATION_not_defined ; /* Cause syntax error */ -`else +`endif module memory_slave_model #( @@ -142,5 +142,3 @@ module memory_slave_model end end endmodule // memory_slave_model - -`endif // !`ifndef SIMULATION |