add wishbone slave with embedded bram

1 files changed, 55 insertions, 0 deletions

diff --git a/design/embedded_bram_slave.v b/design/embedded_bram_slave.v
new file mode 100644
index 0000000..17738af
--- /dev/null
+++ b/design/embedded_bram_slave.v
@@ -0,0 +1,55 @@
+/*
+ * This is very to design/slave.v, although with 1 important difference
+ * - it's meant to be synthesizable (and use iCE40HX8K's embedded RAM).
+ */
+`default_nettype none
+
+`define ADDR_WIDTH ($clog2(MEMORY_BLOCKS) + 8)
+
+module embedded_bram_slave
+  #(
+    parameter MEMORY_BLOCKS = 1, /* 1 block stores 256 16-bit words */
+    parameter WORDS_TO_INITIALIZE = 0,
+    parameter INITIAL_CONTENTS_FILE = "some_file.mem"
+    )
+   (
+    output wire 		   ACK_O,
+    input wire 			   CLK_I,
+    input wire [`ADDR_WIDTH - 1:0] ADR_I,
+    input wire [15:0] 		   DAT_I,
+    output wire [15:0] 		   DAT_O,
+    input wire 			   RST_I,
+    input wire 			   STB_I,
+    input wire 			   WE_I,
+    output wire 		   STALL_O
+    );
+
+   reg [15:0] 			   memory [256 * MEMORY_BLOCKS - 1 : 0];
+
+   generate
+      if (WORDS_TO_INITIALIZE) begin
+	 initial
+	   $readmemb(INITIAL_CONTENTS_FILE, memory, 0, WORDS_TO_INITIALIZE - 1);
+      end
+   endgenerate
+
+   reg [15:0] output_data;
+   reg 	      ack;
+
+   assign DAT_O = output_data;
+   assign ACK_O = ack;
+   assign STALL_O = 0;
+
+   always @ (posedge CLK_I) begin
+      if (RST_I) begin
+	 ack <= 0;
+      end else begin
+	 ack <= STB_I;
+
+	 output_data <= memory[ADR_I];
+
+	 if (STB_I && WE_I)
+	   memory[ADR_I] <= DAT_I;
+      end
+   end // always @ (posedge CLK_I)
+endmodule // embedded_bram_slave