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AGH-engineering-thesis
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Code related to my engineering thesis at AGH University of Science and Technology in Kraków, Poland
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2020-09-07
add wrapped stack machine with bench
Wojciech Kosior
2020-09-07
add intercon module, that encapsulates slave_dispatcher and master_arbiter ↵
Wojciech Kosior
and a bench for it (use adapted operations files from master_arbiter test)
2020-09-07
fix port directions
Wojciech Kosior
2020-09-07
rename intercon to slave_dispatcher (soc module will remporarily stop ↵
Wojciech Kosior
working from this commit on)
2020-09-07
add a wishbone arbiter for 2 masters
Wojciech Kosior
2020-09-07
add wrapper from wb master interface with 32-bit data port to wb interface ↵
Wojciech Kosior
with 16-bit data port together with testbench
2020-09-05
add cond_jump instruction together with bench
Wojciech Kosior
2020-09-05
add jump instruction together with bench
Wojciech Kosior
2020-09-05
add mul instruction together with bench
Wojciech Kosior
2020-09-05
add div instruction together with bench
Wojciech Kosior
2020-09-05
add swap instruction together with bench
Wojciech Kosior
2020-09-05
add sub instruction together with bench
Wojciech Kosior
2020-09-05
add add instruction together with bench
Wojciech Kosior
2020-09-05
add tee instruction together with bench
Wojciech Kosior
2020-09-05
start another attempt for good stack machine design
Wojciech Kosior
2020-09-03
rename tclasm.tcl to tclasm_old.tcl (prepare for redesign of the stack machine)
Wojciech Kosior
2020-09-03
rename stack_machine to stack_machine_old (prepare for redesign of the machine)
Wojciech Kosior
2020-09-03
add the ability to synthesize the design
Wojciech Kosior
2020-09-03
make embedded memory with program code read-only (not strictly needed, but ↵
Wojciech Kosior
protects it from accidental overwriting before reset button is pressed)
2020-09-03
register values immediately after reading the from embedded ram (this is ↵
Wojciech Kosior
required for memories to get inferred)
2020-09-02
add topmost module of the synthesizable design
Wojciech Kosior
2020-09-02
name correction: remove "wb" from "sram_wb_slave"
Wojciech Kosior
2020-09-02
add wishbone slave with embedded bram
Wojciech Kosior
2020-09-02
add wishbone wrapper for sram
Wojciech Kosior
2020-09-02
add tee instruction
Wojciech Kosior
2020-09-01
change horizontal counter initialization on reset
Wojciech Kosior
2020-09-01
whenever we have a big array, signify, that we're using embedded RAM for it
Wojciech Kosior
2020-09-01
start anew
Wojciech Kosior