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2020-09-07rename intercon to slave_dispatcher (soc module will remporarily stop ↵Wojciech Kosior
working from this commit on)
2020-09-07add a wishbone arbiter for 2 mastersWojciech Kosior
2020-09-07add wrapper from wb master interface with 32-bit data port to wb interface ↵Wojciech Kosior
with 16-bit data port together with testbench
2020-09-05add cond_jump instruction together with benchWojciech Kosior
2020-09-05add jump instruction together with benchWojciech Kosior
2020-09-05add mul instruction together with benchWojciech Kosior
2020-09-05add div instruction together with benchWojciech Kosior
2020-09-05add swap instruction together with benchWojciech Kosior
2020-09-05add sub instruction together with benchWojciech Kosior
2020-09-05add add instruction together with benchWojciech Kosior
2020-09-05add tee instruction together with benchWojciech Kosior
2020-09-05start another attempt for good stack machine designWojciech Kosior
2020-09-03rename tclasm.tcl to tclasm_old.tcl (prepare for redesign of the stack machine)Wojciech Kosior
2020-09-03rename stack_machine to stack_machine_old (prepare for redesign of the machine)Wojciech Kosior
2020-09-03add the ability to synthesize the designWojciech Kosior
2020-09-03make embedded memory with program code read-only (not strictly needed, but ↵Wojciech Kosior
protects it from accidental overwriting before reset button is pressed)
2020-09-03register values immediately after reading the from embedded ram (this is ↵Wojciech Kosior
required for memories to get inferred)
2020-09-02add topmost module of the synthesizable designWojciech Kosior
2020-09-02name correction: remove "wb" from "sram_wb_slave"Wojciech Kosior
2020-09-02add wishbone slave with embedded bramWojciech Kosior
2020-09-02add wishbone wrapper for sramWojciech Kosior
2020-09-02add tee instructionWojciech Kosior
2020-09-01change horizontal counter initialization on resetWojciech Kosior
2020-09-01whenever we have a big array, signify, that we're using embedded RAM for itWojciech Kosior
2020-09-01start anewWojciech Kosior
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