AGH-engineering-thesis - Code related to my engineering thesis at AGH University of Science and Technology in Kraków, Poland

Age	Commit message (Expand)	Author
2020-09-03	rename tclasm.tcl to tclasm_old.tcl (prepare for redesign of the stack machine)	Wojciech Kosior
2020-09-03	rename stack_machine to stack_machine_old (prepare for redesign of the machine)	Wojciech Kosior
2020-09-03	add the ability to synthesize the design	Wojciech Kosior
2020-09-03	make embedded memory with program code read-only (not strictly needed, but pr...	Wojciech Kosior
2020-09-03	register values immediately after reading the from embedded ram (this is requ...	Wojciech Kosior
2020-09-02	add topmost module of the synthesizable design	Wojciech Kosior
2020-09-02	name correction: remove "wb" from "sram_wb_slave"	Wojciech Kosior
2020-09-02	add wishbone slave with embedded bram	Wojciech Kosior
2020-09-02	add wishbone wrapper for sram	Wojciech Kosior
2020-09-02	add tee instruction	Wojciech Kosior
2020-09-01	change horizontal counter initialization on reset	Wojciech Kosior
2020-09-01	whenever we have a big array, signify, that we're using embedded RAM for it	Wojciech Kosior
2020-09-01	start anew	Wojciech Kosior