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AgeCommit message (Expand)Author
2020-12-31Add Wishbone datasheetsWojciech Kosior
2020-12-24prepare makefile infrastructure for writing examplesWojciech Kosior
2020-12-21remove double lines in memory map commentsWojciech Kosior
2020-11-23write Wasm code, that can print a number on the screenWojciech Kosior
2020-11-23add unsigned division remainder instructionWojciech Kosior
2020-11-21add miscellaneous module, which controls led2 and button2 and provides a time...Wojciech Kosior
2020-11-21fix typo in commentWojciech Kosior
2020-11-21increase number of wb slaves, that can be attached to the interconWojciech Kosior
2020-11-03incorporate SPI module into main designWojciech Kosior
2020-11-03add spi wishbone slave with a simplified flash memory chip model and a test b...Wojciech Kosior
2020-10-10fix yosys synthesisWojciech Kosior
2020-10-06add some debugging facility inside the cpuWojciech Kosior
2020-10-06add relational operations to stack machineWojciech Kosior
2020-10-05fixes, add_sp instruciton and translation of br instruction from wasmWojciech Kosior
2020-10-05fixes, conditional if-not jump and translation of if-else instruction from wasmWojciech Kosior
2020-09-16add function calling (call, ret and drop instructions) with a testbench + bug...Wojciech Kosior
2020-09-16also enable reading from vga text memoryWojciech Kosior
2020-09-14add ability to make non-aligned loads/stores and loads/stores of 1 or 2 bytes...Wojciech Kosior
2020-09-09enable byte-grained reads and writes through interface_wrapperWojciech Kosior
2020-09-08remove trailing whitespaceWojciech Kosior
2020-09-08use new machine's instructions in synthesisWojciech Kosior
2020-09-07remove old version of stack machine from the projectWojciech Kosior
2020-09-07update soc toplevel module to use new version of stack machineWojciech Kosior
2020-09-07add wrapped stack machine with benchWojciech Kosior
2020-09-07add intercon module, that encapsulates slave_dispatcher and master_arbiter an...Wojciech Kosior
2020-09-07fix port directionsWojciech Kosior
2020-09-07rename intercon to slave_dispatcher (soc module will remporarily stop working...Wojciech Kosior
2020-09-07add a wishbone arbiter for 2 mastersWojciech Kosior
2020-09-07add wrapper from wb master interface with 32-bit data port to wb interface wi...Wojciech Kosior
2020-09-05add cond_jump instruction together with benchWojciech Kosior
2020-09-05add jump instruction together with benchWojciech Kosior
2020-09-05add mul instruction together with benchWojciech Kosior
2020-09-05add div instruction together with benchWojciech Kosior
2020-09-05add swap instruction together with benchWojciech Kosior
2020-09-05add sub instruction together with benchWojciech Kosior
2020-09-05add add instruction together with benchWojciech Kosior
2020-09-05add tee instruction together with benchWojciech Kosior
2020-09-05start another attempt for good stack machine designWojciech Kosior
2020-09-03rename tclasm.tcl to tclasm_old.tcl (prepare for redesign of the stack machine)Wojciech Kosior
2020-09-03rename stack_machine to stack_machine_old (prepare for redesign of the machine)Wojciech Kosior
2020-09-03add the ability to synthesize the designWojciech Kosior
2020-09-03make embedded memory with program code read-only (not strictly needed, but pr...Wojciech Kosior
2020-09-03register values immediately after reading the from embedded ram (this is requ...Wojciech Kosior
2020-09-02add topmost module of the synthesizable designWojciech Kosior
2020-09-02name correction: remove "wb" from "sram_wb_slave"Wojciech Kosior
2020-09-02add wishbone slave with embedded bramWojciech Kosior
2020-09-02add wishbone wrapper for sramWojciech Kosior
2020-09-02add tee instructionWojciech Kosior
2020-09-01change horizontal counter initialization on resetWojciech Kosior
2020-09-01whenever we have a big array, signify, that we're using embedded RAM for itWojciech Kosior
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