AGH-engineering-thesis - Code related to my engineering thesis at AGH University of Science and Technology in Kraków, Poland

Age	Commit message (Expand)	Author
2020-09-07	add a wishbone arbiter for 2 masters	Wojciech Kosior
2020-09-07	add wrapper from wb master interface with 32-bit data port to wb interface wi...	Wojciech Kosior
2020-09-05	add cond_jump instruction together with bench	Wojciech Kosior
2020-09-05	add jump instruction together with bench	Wojciech Kosior
2020-09-05	add mul instruction together with bench	Wojciech Kosior
2020-09-05	add div instruction together with bench	Wojciech Kosior
2020-09-05	put procedures in tclasm.tcl in some order	Wojciech Kosior
2020-09-05	add swap instruction together with bench	Wojciech Kosior
2020-09-05	add sub instruction together with bench	Wojciech Kosior
2020-09-05	add add instruction together with bench	Wojciech Kosior
2020-09-05	add tee instruction together with bench	Wojciech Kosior
2020-09-05	add Makefile target, that runs all short tests	Wojciech Kosior
2020-09-05	add tclasm multiinstructions (instructions, that possibly translate to more t...	Wojciech Kosior
2020-09-05	add load_store bench for new stack machine	Wojciech Kosior
2020-09-05	add first simple bench for new stack machine	Wojciech Kosior
2020-09-05	start another attempt for good stack machine design	Wojciech Kosior
2020-09-05	replace fixed-width constant from now-parameterized wb slave model	Wojciech Kosior
2020-09-04	add bench for parametrized instantiation of models	Wojciech Kosior
2020-09-04	fix master after parametrization	Wojciech Kosior
2020-09-04	enable parametrizable address and data widths for master model	Wojciech Kosior
2020-09-04	enable parametrizable address and data widths for slave model	Wojciech Kosior
2020-09-03	rename tclasm.tcl to tclasm_old.tcl (prepare for redesign of the stack machine)	Wojciech Kosior
2020-09-03	treat embedded RAM as read-only in test bench	Wojciech Kosior
2020-09-03	rename stack_machine to stack_machine_old (prepare for redesign of the machine)	Wojciech Kosior
2020-09-03	add the ability to synthesize the design	Wojciech Kosior
2020-09-03	make embedded memory with program code read-only (not strictly needed, but pr...	Wojciech Kosior
2020-09-03	register values immediately after reading the from embedded ram (this is requ...	Wojciech Kosior
2020-09-02	remove unnecessary complexity from preprocessor error throwing	Wojciech Kosior
2020-09-02	don't exceed 80 characters in a line	Wojciech Kosior
2020-09-02	add a VGA-based bench for entire sock	Wojciech Kosior
2020-09-02	add topmost module of the synthesizable design	Wojciech Kosior
2020-09-02	name correction: remove "wb" from "sram_wb_slave"	Wojciech Kosior
2020-09-02	add bench for embedded ram wishbone slave	Wojciech Kosior
2020-09-02	add wishbone slave with embedded bram	Wojciech Kosior
2020-09-02	add bench for wishbone sram wrapper	Wojciech Kosior
2020-09-02	add wishbone wrapper for sram	Wojciech Kosior
2020-09-02	add bench for cond_jump instruction	Wojciech Kosior
2020-09-02	add bench for swap instruction	Wojciech Kosior
2020-09-02	remove old debugging code	Wojciech Kosior
2020-09-02	Add bench for tee instruction	Wojciech Kosior
2020-09-02	add bench for jump instruction	Wojciech Kosior
2020-09-02	add tee instruction	Wojciech Kosior
2020-09-02	add cond_jump instruction, rework jump instruction	Wojciech Kosior
2020-09-01	remove old debugging code	Wojciech Kosior
2020-09-01	fix line counting in test model (avoid having picture shifted 1 line down on ...	Wojciech Kosior
2020-09-01	change horizontal counter initialization on reset	Wojciech Kosior
2020-09-01	whenever we have a big array, signify, that we're using embedded RAM for it	Wojciech Kosior
2020-09-01	start anew	Wojciech Kosior
2020-07-24	add license	Wojciech Kosior
2020-07-18	after reset copy data from spi flash chip to sram	Wojciech Kosior