aboutsummaryrefslogtreecommitdiff
path: root/tests/slave_dispatcher/test.v
diff options
context:
space:
mode:
Diffstat (limited to 'tests/slave_dispatcher/test.v')
-rw-r--r--tests/slave_dispatcher/test.v12
1 files changed, 12 insertions, 0 deletions
diff --git a/tests/slave_dispatcher/test.v b/tests/slave_dispatcher/test.v
index d29b05c..49c03ef 100644
--- a/tests/slave_dispatcher/test.v
+++ b/tests/slave_dispatcher/test.v
@@ -20,6 +20,7 @@ module slave_dispatcher_test();
wire [19:0] M_ADR_O;
wire [15:0] M_DAT_I;
wire [15:0] M_DAT_O;
+ wire M_SEL_O; /* Ignored, assumed always high */
wire M_STB_O;
wire M_CYC_O;
wire M_WE_O;
@@ -30,6 +31,7 @@ module slave_dispatcher_test();
wire [17:0] S0_ADR_I, S1_ADR_I, S2_ADR_I, S3_ADR_I;
wire [15:0] S0_DAT_I, S1_DAT_I, S2_DAT_I, S3_DAT_I;
wire [15:0] S0_DAT_O, S1_DAT_O, S2_DAT_O, S3_DAT_O;
+ wire S0_SEL_I, S1_SEL_I, S2_SEL_I, S3_SEL_I; /* Always high */
wire S0_RST_I, S1_RST_I, S2_RST_I, S3_RST_I;
wire S0_STB_I, S1_STB_I, S2_STB_I, S3_STB_I;
wire S0_WE_I, S1_WE_I, S2_WE_I, S3_WE_I;
@@ -57,6 +59,7 @@ module slave_dispatcher_test();
.ADR_O(M_ADR_O),
.DAT_I(M_DAT_I),
.DAT_O(M_DAT_O),
+ .SEL_O(M_SEL_O),
.RST_I(RST),
.STB_O(M_STB_O),
.CYC_O(M_CYC_O),
@@ -76,6 +79,7 @@ module slave_dispatcher_test();
.ADR_I(S0_ADR_I),
.DAT_I(S0_DAT_I),
.DAT_O(S0_DAT_O),
+ .SEL_I(S0_SEL_I),
.RST_I(RST),
.STB_I(S0_STB_I),
.WE_I(S0_WE_I),
@@ -92,6 +96,7 @@ module slave_dispatcher_test();
.ADR_I(S1_ADR_I),
.DAT_I(S1_DAT_I),
.DAT_O(S1_DAT_O),
+ .SEL_I(S1_SEL_I),
.RST_I(RST),
.STB_I(S1_STB_I),
.WE_I(S1_WE_I),
@@ -108,6 +113,7 @@ module slave_dispatcher_test();
.ADR_I(S2_ADR_I),
.DAT_I(S2_DAT_I),
.DAT_O(S2_DAT_O),
+ .SEL_I(S2_SEL_I),
.RST_I(RST),
.STB_I(S2_STB_I),
.WE_I(S2_WE_I),
@@ -124,6 +130,7 @@ module slave_dispatcher_test();
.ADR_I(S3_ADR_I),
.DAT_I(S3_DAT_I),
.DAT_O(S3_DAT_O),
+ .SEL_I(S3_SEL_I),
.RST_I(RST),
.STB_I(S3_STB_I),
.WE_I(S3_WE_I),
@@ -185,6 +192,11 @@ module slave_dispatcher_test();
assign S_COMBINED_STB_I = M_STB_O && M_CYC_O;
assign S_COMBINED_WE_I = M_WE_O;
+ assign S0_SEL_I = 1;
+ assign S1_SEL_I = 1;
+ assign S2_SEL_I = 1;
+ assign S3_SEL_I = 1;
+
integer i;
initial begin