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-rw-r--r--tests/self_32bit_word/test.v7
1 files changed, 7 insertions, 0 deletions
diff --git a/tests/self_32bit_word/test.v b/tests/self_32bit_word/test.v
index 804b4d3..871fe0c 100644
--- a/tests/self_32bit_word/test.v
+++ b/tests/self_32bit_word/test.v
@@ -19,6 +19,7 @@ module self_32bit_test();
wire [21:0] M_ADR_O;
wire [31:0] M_DAT_I;
wire [31:0] M_DAT_O;
+ wire [3:0] M_SEL_O;
wire M_RST_I;
wire M_STB_O;
wire M_CYC_O;
@@ -30,6 +31,7 @@ module self_32bit_test();
wire [21:0] S_ADR_I;
wire [31:0] S_DAT_I;
wire [31:0] S_DAT_O;
+ wire [3:0] S_SEL_I;
wire S_RST_I;
wire S_STB_I;
wire S_WE_I;
@@ -42,6 +44,7 @@ module self_32bit_test();
#(
.MASTER_NR(0),
.WORD_SIZE(4),
+ .SEL_LINES(4),
.ADR_BITS(22),
.OPERATIONS_FILE("operations.mem"),
.OPERATIONS_COUNT(`MASTER_OPERATIONS_COUNT)
@@ -52,6 +55,7 @@ module self_32bit_test();
.ADR_O(M_ADR_O),
.DAT_I(M_DAT_I),
.DAT_O(M_DAT_O),
+ .SEL_O(M_SEL_O),
.RST_I(M_RST_I),
.STB_O(M_STB_O),
.CYC_O(M_CYC_O),
@@ -65,6 +69,7 @@ module self_32bit_test();
#(
.SLAVE_NR(0),
.WORD_SIZE(4),
+ .SEL_LINES(4),
.ADR_BITS(22)
) slave
(
@@ -73,6 +78,7 @@ module self_32bit_test();
.ADR_I(S_ADR_I),
.DAT_I(S_DAT_I),
.DAT_O(S_DAT_O),
+ .SEL_I(S_SEL_I),
.RST_I(S_RST_I),
.STB_I(S_STB_I),
.WE_I(S_WE_I),
@@ -91,6 +97,7 @@ module self_32bit_test();
assign S_CLK_I = CLK;
assign S_ADR_I = M_ADR_O;
assign S_DAT_I = M_DAT_O;
+ assign S_SEL_I = M_SEL_O;
assign S_RST_I = RST;
assign S_STB_I = M_STB_O && M_CYC_O;
assign S_WE_I = M_WE_O;