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AGH-engineering-thesis
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Code related to my engineering thesis at AGH University of Science and Technology in Kraków, Poland
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2020-09-19
initial work towards translating wasm to stack machine (with a provisional ↵
Wojciech Kosior
bench)
2020-09-16
add function calling (call, ret and drop instructions) with a testbench + ↵
Wojciech Kosior
bugfix in stack machine
2020-09-16
fix old comments
Wojciech Kosior
2020-09-14
update comment to reflect changes
Wojciech Kosior
2020-09-14
add ability to make non-aligned loads/stores and loads/stores of 1 or 2 ↵
Wojciech Kosior
bytes together with test bench
2020-09-14
fix outdated information in comments
Wojciech Kosior
2020-09-09
enable byte-grained reads and writes through interface_wrapper
Wojciech Kosior
2020-09-08
enable slave and master models to use SEL_ signal
Wojciech Kosior
2020-09-08
remove trailing whitespace
Wojciech Kosior
2020-09-08
modernize the build (test) system
Wojciech Kosior
2020-09-08
remove old debugging code
Wojciech Kosior
2020-09-07
remove old version of stack machine from the project
Wojciech Kosior
2020-09-07
update soc toplevel module to use new version of stack machine
Wojciech Kosior
2020-09-07
add wrapped stack machine with bench
Wojciech Kosior
2020-09-07
add intercon module, that encapsulates slave_dispatcher and master_arbiter ↵
Wojciech Kosior
and a bench for it (use adapted operations files from master_arbiter test)
2020-09-07
rename intercon to slave_dispatcher (soc module will remporarily stop ↵
Wojciech Kosior
working from this commit on)
2020-09-07
add a wishbone arbiter for 2 masters
Wojciech Kosior
2020-09-07
add wrapper from wb master interface with 32-bit data port to wb interface ↵
Wojciech Kosior
with 16-bit data port together with testbench
2020-09-05
add cond_jump instruction together with bench
Wojciech Kosior
2020-09-05
add jump instruction together with bench
Wojciech Kosior
2020-09-05
add mul instruction together with bench
Wojciech Kosior
2020-09-05
add div instruction together with bench
Wojciech Kosior
2020-09-05
add swap instruction together with bench
Wojciech Kosior
2020-09-05
add sub instruction together with bench
Wojciech Kosior
2020-09-05
add add instruction together with bench
Wojciech Kosior
2020-09-05
add tee instruction together with bench
Wojciech Kosior
2020-09-05
add tclasm multiinstructions (instructions, that possibly translate to more ↵
Wojciech Kosior
than one)
2020-09-05
add load_store bench for new stack machine
Wojciech Kosior
2020-09-05
add first simple bench for new stack machine
Wojciech Kosior
2020-09-04
add bench for parametrized instantiation of models
Wojciech Kosior
2020-09-03
rename tclasm.tcl to tclasm_old.tcl (prepare for redesign of the stack machine)
Wojciech Kosior
2020-09-03
treat embedded RAM as read-only in test bench
Wojciech Kosior
2020-09-03
rename stack_machine to stack_machine_old (prepare for redesign of the machine)
Wojciech Kosior
2020-09-02
add a VGA-based bench for entire sock
Wojciech Kosior
2020-09-02
name correction: remove "wb" from "sram_wb_slave"
Wojciech Kosior
2020-09-02
add bench for embedded ram wishbone slave
Wojciech Kosior
2020-09-02
add bench for wishbone sram wrapper
Wojciech Kosior
2020-09-02
add bench for cond_jump instruction
Wojciech Kosior
2020-09-02
add bench for swap instruction
Wojciech Kosior
2020-09-02
remove old debugging code
Wojciech Kosior
2020-09-02
Add bench for tee instruction
Wojciech Kosior
2020-09-02
add bench for jump instruction
Wojciech Kosior
2020-09-01
remove old debugging code
Wojciech Kosior
2020-09-01
fix line counting in test model (avoid having picture shifted 1 line down on ↵
Wojciech Kosior
virtual display)
2020-09-01
start anew
Wojciech Kosior