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| author | Wojciech Kosior <kwojtus@protonmail.com> | 2020-09-08 17:46:12 +0200 |
|---|---|---|
| committer | Wojciech Kosior <kwojtus@protonmail.com> | 2020-09-08 17:46:12 +0200 |
| commit | cd0421f0c30fcbe557c89f0fe7cd1b1e5ea42f9c (patch) | |
| tree | feb49818e92940cd20586dcb23951fe04e54a2f2 /tests | |
| parent | dfcd082cd2290fb39d8cb322f2ab70f0e8752ef7 (diff) | |
| download | AGH-engineering-thesis-cd0421f0c30fcbe557c89f0fe7cd1b1e5ea42f9c.tar.gz AGH-engineering-thesis-cd0421f0c30fcbe557c89f0fe7cd1b1e5ea42f9c.zip | |
remove trailing whitespace
Diffstat (limited to 'tests')
| -rw-r--r-- | tests/div/test.v | 2 | ||||
| -rw-r--r-- | tests/embedded_bram_slave/test.v | 2 | ||||
| -rw-r--r-- | tests/self/test.v | 2 | ||||
| -rw-r--r-- | tests/self_32bit_word/test.v | 2 |
4 files changed, 4 insertions, 4 deletions
diff --git a/tests/div/test.v b/tests/div/test.v index f360ebd..a98f084 100644 --- a/tests/div/test.v +++ b/tests/div/test.v @@ -54,7 +54,7 @@ module div_test(); dividend <= 15; divisor <= 3; progress <= progress + 1; - end else begin + end else begin if (done) begin if (dividend / divisor === quotient && dividend % divisor === remainder) begin `DBG(("%0d/%0d computed as %0d r %0d", dividend, divisor, quotient, remainder)); diff --git a/tests/embedded_bram_slave/test.v b/tests/embedded_bram_slave/test.v index 0ee2833..94225bd 100644 --- a/tests/embedded_bram_slave/test.v +++ b/tests/embedded_bram_slave/test.v @@ -68,7 +68,7 @@ module embedded_bram_test(); .MEMORY_BLOCKS(2), .WORDS_TO_INITIALIZE(`ROM_WORDS_COUNT), .INITIAL_CONTENTS_FILE("rom.mem") - ) slave + ) slave ( .ACK_O(S_ACK_O), .CLK_I(S_CLK_I), diff --git a/tests/self/test.v b/tests/self/test.v index b92a63e..8eb0617 100644 --- a/tests/self/test.v +++ b/tests/self/test.v @@ -61,7 +61,7 @@ module self_test(); memory_slave_model #( .SLAVE_NR(0) - ) slave + ) slave ( .ACK_O(S_ACK_O), .CLK_I(S_CLK_I), diff --git a/tests/self_32bit_word/test.v b/tests/self_32bit_word/test.v index 86ed660..804b4d3 100644 --- a/tests/self_32bit_word/test.v +++ b/tests/self_32bit_word/test.v @@ -66,7 +66,7 @@ module self_32bit_test(); .SLAVE_NR(0), .WORD_SIZE(4), .ADR_BITS(22) - ) slave + ) slave ( .ACK_O(S_ACK_O), .CLK_I(S_CLK_I), |