rename intercon to slave_dispatcher (soc module will remporarily stop working from this commit on)

2 files changed, 39 insertions, 46 deletions

diff --git a/tests/intercon/operations.memv b/tests/slave_dispatcher/operations.memv
index 8785d5c..8785d5c 100644
--- a/tests/intercon/operations.memv
+++ b/tests/slave_dispatcher/operations.memv
diff --git a/tests/intercon/test.v b/tests/slave_dispatcher/test.v
index 1945f44..d29b05c 100644
--- a/tests/intercon/test.v
+++ b/tests/slave_dispatcher/test.v
@@ -12,13 +12,14 @@
 ; /* Cause syntax error */
 `endif
 
-module intercon_test();
+module slave_dispatcher_test();
+   reg 	       CLK;
+   reg 	       RST;
+
    wire        M_ACK_I;
-   wire        M_CLK_I;
    wire [19:0] M_ADR_O;
    wire [15:0] M_DAT_I;
    wire [15:0] M_DAT_O;
-   wire        M_RST_I;
    wire        M_STB_O;
    wire        M_CYC_O;
    wire        M_WE_O;
@@ -34,8 +35,13 @@ module intercon_test();
    wire        S0_WE_I,    S1_WE_I,    S2_WE_I,    S3_WE_I;
    wire        S0_STALL_O, S1_STALL_O, S2_STALL_O, S3_STALL_O;
 
-   reg 	       CLK;
-   reg 	       RST;
+   wire        S_COMBINED_ACK_O;
+   wire [19:0] S_COMBINED_ADR_I;
+   wire [15:0] S_COMBINED_DAT_I;
+   wire [15:0] S_COMBINED_DAT_O;
+   wire        S_COMBINED_STB_I;
+   wire        S_COMBINED_WE_I;
+   wire        S_COMBINED_STALL_O;
 
    /* Non-wishbone */
    wire        M_finished;
@@ -47,11 +53,11 @@ module intercon_test();
        ) master
        (
 	.ACK_I(M_ACK_I),
- 	.CLK_I(M_CLK_I),
+ 	.CLK_I(CLK),
 	.ADR_O(M_ADR_O),
 	.DAT_I(M_DAT_I),
 	.DAT_O(M_DAT_O),
- 	.RST_I(M_RST_I),
+ 	.RST_I(RST),
 	.STB_O(M_STB_O),
 	.CYC_O(M_CYC_O),
 	.WE_O(M_WE_O),
@@ -66,11 +72,11 @@ module intercon_test();
        ) slave0
        (
 	.ACK_O(S0_ACK_O),
-      	.CLK_I(S0_CLK_I),
+      	.CLK_I(CLK),
 	.ADR_I(S0_ADR_I),
 	.DAT_I(S0_DAT_I),
 	.DAT_O(S0_DAT_O),
-      	.RST_I(S0_RST_I),
+      	.RST_I(RST),
       	.STB_I(S0_STB_I),
       	.WE_I(S0_WE_I),
 	.STALL_O(S0_STALL_O)
@@ -82,11 +88,11 @@ module intercon_test();
        ) slave1
        (
 	.ACK_O(S1_ACK_O),
-      	.CLK_I(S1_CLK_I),
+      	.CLK_I(CLK),
 	.ADR_I(S1_ADR_I),
 	.DAT_I(S1_DAT_I),
 	.DAT_O(S1_DAT_O),
-      	.RST_I(S1_RST_I),
+      	.RST_I(RST),
       	.STB_I(S1_STB_I),
       	.WE_I(S1_WE_I),
 	.STALL_O(S1_STALL_O)
@@ -98,11 +104,11 @@ module intercon_test();
        ) slave2
        (
 	.ACK_O(S2_ACK_O),
-      	.CLK_I(S2_CLK_I),
+      	.CLK_I(CLK),
 	.ADR_I(S2_ADR_I),
 	.DAT_I(S2_DAT_I),
 	.DAT_O(S2_DAT_O),
-      	.RST_I(S2_RST_I),
+      	.RST_I(RST),
       	.STB_I(S2_STB_I),
       	.WE_I(S2_WE_I),
 	.STALL_O(S2_STALL_O)
@@ -114,73 +120,71 @@ module intercon_test();
        ) slave3
        (
 	.ACK_O(S3_ACK_O),
-      	.CLK_I(S3_CLK_I),
+      	.CLK_I(CLK),
 	.ADR_I(S3_ADR_I),
 	.DAT_I(S3_DAT_I),
 	.DAT_O(S3_DAT_O),
-      	.RST_I(S3_RST_I),
+      	.RST_I(RST),
       	.STB_I(S3_STB_I),
       	.WE_I(S3_WE_I),
 	.STALL_O(S3_STALL_O)
 	);
 
-   intercon intercon
+   slave_dispatcher dispatcher
      (
       .CLK(CLK),
       .RST(RST),
 
       .S0_ACK_O(S0_ACK_O),
-      .S0_CLK_I(S0_CLK_I),
       .S0_ADR_I(S0_ADR_I),
       .S0_DAT_I(S0_DAT_I),
       .S0_DAT_O(S0_DAT_O),
-      .S0_RST_I(S0_RST_I),
       .S0_STB_I(S0_STB_I),
       .S0_WE_I(S0_WE_I),
       .S0_STALL_O(S0_STALL_O),
 
       .S1_ACK_O(S1_ACK_O),
-      .S1_CLK_I(S1_CLK_I),
       .S1_ADR_I(S1_ADR_I),
       .S1_DAT_I(S1_DAT_I),
       .S1_DAT_O(S1_DAT_O),
-      .S1_RST_I(S1_RST_I),
       .S1_STB_I(S1_STB_I),
       .S1_WE_I(S1_WE_I),
       .S1_STALL_O(S1_STALL_O),
 
       .S2_ACK_O(S2_ACK_O),
-      .S2_CLK_I(S2_CLK_I),
       .S2_ADR_I(S2_ADR_I),
       .S2_DAT_I(S2_DAT_I),
       .S2_DAT_O(S2_DAT_O),
-      .S2_RST_I(S2_RST_I),
       .S2_STB_I(S2_STB_I),
       .S2_WE_I(S2_WE_I),
       .S2_STALL_O(S2_STALL_O),
 
       .S3_ACK_O(S3_ACK_O),
-      .S3_CLK_I(S3_CLK_I),
       .S3_ADR_I(S3_ADR_I),
       .S3_DAT_I(S3_DAT_I),
       .S3_DAT_O(S3_DAT_O),
-      .S3_RST_I(S3_RST_I),
       .S3_STB_I(S3_STB_I),
       .S3_WE_I(S3_WE_I),
       .S3_STALL_O(S3_STALL_O),
 
-      .M_ACK_I(M_ACK_I),
-      .M_CLK_I(M_CLK_I),
-      .M_ADR_O(M_ADR_O),
-      .M_DAT_O(M_DAT_O),
-      .M_DAT_I(M_DAT_I),
-      .M_RST_I(M_RST_I),
-      .M_STB_O(M_STB_O),
-      .M_CYC_O(M_CYC_O),
-      .M_WE_O(M_WE_O),
-      .M_STALL_I(M_STALL_I)
+      .S_COMBINED_ACK_O(S_COMBINED_ACK_O),
+      .S_COMBINED_ADR_I(S_COMBINED_ADR_I),
+      .S_COMBINED_DAT_I(S_COMBINED_DAT_I),
+      .S_COMBINED_DAT_O(S_COMBINED_DAT_O),
+      .S_COMBINED_STB_I(S_COMBINED_STB_I),
+      .S_COMBINED_WE_I(S_COMBINED_WE_I),
+      .S_COMBINED_STALL_O(S_COMBINED_STALL_O)
       );
 
+   assign M_ACK_I = S_COMBINED_ACK_O;
+   assign M_DAT_I = S_COMBINED_DAT_O;
+   assign M_STALL_I = S_COMBINED_STALL_O;
+
+   assign S_COMBINED_ADR_I = M_ADR_O;
+   assign S_COMBINED_DAT_I = M_DAT_O;
+   assign S_COMBINED_STB_I = M_STB_O && M_CYC_O;
+   assign S_COMBINED_WE_I = M_WE_O;
+
    integer     i;
 
    initial begin
@@ -197,20 +201,9 @@ module intercon_test();
 
 	 if (M_finished)
 	   $finish;
-
-	 /*
-	  * I should delete this debugging code, but from time to time
-	  * it proves so handy, that I just can't do it :/
-	  */
-	 // if (!CLK)
-	 //   `DBG(({"M_CYC_O: %d   M_STB_O: %d   M_ACK_I: %d   M_STALL_I: %d   ",
-	 //  	  "sla: %d   sa: %d   ca: %d   RST: %b"},
-	 //  	 M_CYC_O, M_STB_O, M_ACK_I, M_STALL_I,
-	 //  	 intercon.slave_last_accessed, intercon.slave_accessed,
-	 // 	 intercon.commands_awaiting, intercon.RST));
       end
 
       $display("error: master hasn't finished its opertaions in 300 ticks");
       $finish;
    end
-endmodule // intercon_test
+endmodule // slave_dispatcher_test