| Age | Commit message (Expand) | Author |
|---|---|---|
| 2020-09-02 | add topmost module of the synthesizable design | Wojciech Kosior |
| 2020-09-02 | name correction: remove "wb" from "sram_wb_slave" | Wojciech Kosior |
| 2020-09-02 | add wishbone slave with embedded bram | Wojciech Kosior |
| 2020-09-02 | add wishbone wrapper for sram | Wojciech Kosior |
| 2020-09-02 | add tee instruction | Wojciech Kosior |
| 2020-09-01 | change horizontal counter initialization on reset | Wojciech Kosior |
| 2020-09-01 | whenever we have a big array, signify, that we're using embedded RAM for it | Wojciech Kosior |
| 2020-09-01 | start anew | Wojciech Kosior |
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index : AGH-engineering-thesis | |
| Code related to my engineering thesis at AGH University of Science and Technology in Kraków, Poland |
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