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| author | Wojciech Kosior <kwojtus@protonmail.com> | 2020-09-08 21:00:13 +0200 |
|---|---|---|
| committer | Wojciech Kosior <kwojtus@protonmail.com> | 2020-09-08 21:00:13 +0200 |
| commit | bc43ceac936b48fdccfcac33e172e176273d504f (patch) | |
| tree | de2723df14a512c214d0fb991a183c363fae042a /tests/embedded_bram_slave | |
| parent | cd0421f0c30fcbe557c89f0fe7cd1b1e5ea42f9c (diff) | |
| download | AGH-engineering-thesis-bc43ceac936b48fdccfcac33e172e176273d504f.tar.gz AGH-engineering-thesis-bc43ceac936b48fdccfcac33e172e176273d504f.zip | |
enable slave and master models to use SEL_ signal
Diffstat (limited to 'tests/embedded_bram_slave')
| -rw-r--r-- | tests/embedded_bram_slave/test.v | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/tests/embedded_bram_slave/test.v b/tests/embedded_bram_slave/test.v index 94225bd..3671992 100644 --- a/tests/embedded_bram_slave/test.v +++ b/tests/embedded_bram_slave/test.v @@ -23,6 +23,7 @@ module embedded_bram_test(); wire [19:0] M_ADR_O; wire [15:0] M_DAT_I; wire [15:0] M_DAT_O; + wire M_SEL_O; /* Ignored, assumed always high */ wire M_RST_I; wire M_STB_O; wire M_CYC_O; @@ -54,6 +55,7 @@ module embedded_bram_test(); .ADR_O(M_ADR_O), .DAT_I(M_DAT_I), .DAT_O(M_DAT_O), + .SEL_O(M_SEL_O), .RST_I(M_RST_I), .STB_O(M_STB_O), .CYC_O(M_CYC_O), |