| Age | Commit message (Expand) | Author |
|---|---|---|
| 2020-09-08 | enable slave and master models to use SEL_ signal | Wojciech Kosior |
| 2020-09-08 | remove trailing whitespace | Wojciech Kosior |
| 2020-09-08 | modernize the build (test) system | Wojciech Kosior |
| 2020-09-03 | treat embedded RAM as read-only in test bench | Wojciech Kosior |
| 2020-09-02 | add bench for embedded ram wishbone slave | Wojciech Kosior |
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index : AGH-engineering-thesis | |
| code related to my engineering thesis at AGH University of Science and Technology in Kraków, Poland |
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