AGH-engineering-thesis - Code related to my engineering thesis at AGH University of Science and Technology in Kraków, Poland

Age	Commit message (Expand)	Author
2020-12-29	add the ability to include additional data at the end of bitstream image and ...	Wojciech Kosior
2020-12-24	prepare makefile infrastructure for writing examples	Wojciech Kosior
2020-11-03	incorporate SPI module into main design	Wojciech Kosior
2020-11-03	add spi wishbone slave with a simplified flash memory chip model and a test b...	Wojciech Kosior
2020-09-09	fix verification when SEL_O != 4'b1111	Wojciech Kosior
2020-09-08	enable slave and master models to use SEL_ signal	Wojciech Kosior
2020-09-08	remove trailing whitespace	Wojciech Kosior
2020-09-05	replace fixed-width constant from now-parameterized wb slave model	Wojciech Kosior
2020-09-04	fix master after parametrization	Wojciech Kosior
2020-09-04	enable parametrizable address and data widths for master model	Wojciech Kosior
2020-09-04	enable parametrizable address and data widths for slave model	Wojciech Kosior
2020-09-02	remove unnecessary complexity from preprocessor error throwing	Wojciech Kosior
2020-09-02	add bench for wishbone sram wrapper	Wojciech Kosior
2020-09-01	fix line counting in test model (avoid having picture shifted 1 line down on ...	Wojciech Kosior
2020-09-01	start anew	Wojciech Kosior