diff options
| author | Wojciech Kosior <kwojtus@protonmail.com> | 2020-09-08 17:46:12 +0200 |
|---|---|---|
| committer | Wojciech Kosior <kwojtus@protonmail.com> | 2020-09-08 17:46:12 +0200 |
| commit | cd0421f0c30fcbe557c89f0fe7cd1b1e5ea42f9c (patch) | |
| tree | feb49818e92940cd20586dcb23951fe04e54a2f2 /models | |
| parent | dfcd082cd2290fb39d8cb322f2ab70f0e8752ef7 (diff) | |
| download | AGH-engineering-thesis-cd0421f0c30fcbe557c89f0fe7cd1b1e5ea42f9c.tar.gz AGH-engineering-thesis-cd0421f0c30fcbe557c89f0fe7cd1b1e5ea42f9c.zip | |
remove trailing whitespace
Diffstat (limited to 'models')
| -rw-r--r-- | models/master.v | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/models/master.v b/models/master.v index 85656f3..1793fa8 100644 --- a/models/master.v +++ b/models/master.v @@ -1,6 +1,6 @@ /* * A wishbone slave testing module (a "mock") - * + * * It performs a sequence of wishbone writes, reads and waits based on contents * of provided .mem file. It prints error messages whenever the value it reads * if different from the one it expects. @@ -42,7 +42,7 @@ module master_model parameter WORD_BITS = 8 * WORD_SIZE; - parameter + parameter OP_READ = 0, OP_WRITE = 1, OP_WAIT = 2, /* Keep CYC_O high, but STB_O low for 1 tick */ @@ -75,7 +75,7 @@ module master_model j++; end - + if (operations[3*i][1:0] == OP_WRITE) begin was_read[j] <= 0; expected_data[j] <= {(8 * WORD_SIZE - 1){1'bx}}; @@ -112,7 +112,7 @@ module master_model assign current_op_adr = operations[3*operations_performed + 1][ADR_BITS - 1 : 0]; assign current_op_data - = operations[3*operations_performed + 2][WORD_BITS - 1 : 0]; + = operations[3*operations_performed + 2][WORD_BITS - 1 : 0]; assign operation_successful = operations_performed < OPERATIONS_COUNT && |