index
:
AGH-engineering-thesis
master
Code related to my engineering thesis at AGH University of Science and Technology in Kraków, Poland
about
summary
refs
log
tree
commit
diff
log msg
author
committer
range
Age
Commit message (
Collapse
)
Author
2021-06-25
signify README is outdated
HEAD
master
Wojtek Kosior
2020-12-31
Add Wishbone datasheets
Wojciech Kosior
2020-12-29
add the ability to include additional data at the end of bitstream image and ↵
Wojciech Kosior
prepare an example, that reads thic data through SPI and displays it
2020-12-29
add a C program for translating binary files to format understood by Verilog
Wojciech Kosior
2020-12-29
fix align values
Wojciech Kosior
2020-12-28
also add a wasm version of example1 for comparison
Wojciech Kosior
2020-12-28
add a tclasm version of example2
Wojciech Kosior
2020-12-28
small change in text outputted during simulation
Wojciech Kosior
2020-12-24
add example, that measures time and prints it to screen
Wojciech Kosior
2020-12-24
fix typo
Wojciech Kosior
2020-12-24
prepare makefile infrastructure for writing examples
Wojciech Kosior
2020-12-21
remove double lines in memory map comments
Wojciech Kosior
2020-11-23
write Wasm code, that can print a number on the screen
Wojciech Kosior
2020-11-23
add unsigned division remainder instruction
Wojciech Kosior
2020-11-21
add miscellaneous module, which controls led2 and button2 and provides a ↵
Wojciech Kosior
timer; include a testbench for timer and led
2020-11-21
stop make from automatically deleting generated .mem files
Wojciech Kosior
2020-11-21
fix typo in comment
Wojciech Kosior
2020-11-21
increase number of wb slaves, that can be attached to the intercon
Wojciech Kosior
2020-11-03
incorporate SPI module into main design
Wojciech Kosior
2020-11-03
add spi wishbone slave with a simplified flash memory chip model and a test ↵
Wojciech Kosior
bench
2020-10-10
fix yosys synthesis
Wojciech Kosior
2020-10-08
translate webasm block of instructions + put instruction names as comments ↵
Wojciech Kosior
in generated code
2020-10-06
add translation of relational operations and loops
Wojciech Kosior
2020-10-06
add some debugging facility inside the cpu
Wojciech Kosior
2020-10-06
add relational operations to stack machine
Wojciech Kosior
2020-10-06
add translation of br_if instruction
Wojciech Kosior
2020-10-05
fixes, add_sp instruciton and translation of br instruction from wasm
Wojciech Kosior
2020-10-05
fixes, conditional if-not jump and translation of if-else instruction from wasm
Wojciech Kosior
2020-09-22
perform type checking of translated instructions
Wojciech Kosior
2020-09-22
on 'make clean' also delete .mem files compiled from .wasm
Wojciech Kosior
2020-09-21
make running tests through Makefile more comfortable
Wojciech Kosior
2020-09-21
point out the fact, that only one value type is supported for now
Wojciech Kosior
2020-09-21
use function pointer array in Wasm opcode translation
Wojciech Kosior
2020-09-21
enable translation of few arithmetic operations (testbench included)
Wojciech Kosior
2020-09-21
fix memory verification in wasm_compile tests
Wojciech Kosior
2020-09-21
fix leb decoding
Wojciech Kosior
2020-09-21
put function call wasm_compile test in separate bench
Wojciech Kosior
2020-09-21
prepare to perform wasm_compile tests a bit different from stack_machine tests
Wojciech Kosior
2020-09-19
initial work towards translating wasm to stack machine (with a provisional ↵
Wojciech Kosior
bench)
2020-09-16
add function calling (call, ret and drop instructions) with a testbench + ↵
Wojciech Kosior
bugfix in stack machine
2020-09-16
also enable reading from vga text memory
Wojciech Kosior
2020-09-16
fix old comments
Wojciech Kosior
2020-09-14
update comment to reflect changes
Wojciech Kosior
2020-09-14
add ability to make non-aligned loads/stores and loads/stores of 1 or 2 ↵
Wojciech Kosior
bytes together with test bench
2020-09-14
fix outdated information in comments
Wojciech Kosior
2020-09-09
enable byte-grained reads and writes through interface_wrapper
Wojciech Kosior
2020-09-09
fix verification when SEL_O != 4'b1111
Wojciech Kosior
2020-09-08
enable slave and master models to use SEL_ signal
Wojciech Kosior
2020-09-08
remove trailing whitespace
Wojciech Kosior
2020-09-08
Update README
Wojciech Kosior
[next]