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-rw-r--r--Makefile5
-rw-r--r--design/stack_machine.v2
2 files changed, 6 insertions, 1 deletions
diff --git a/Makefile b/Makefile
index dff217c..39f1f1b 100644
--- a/Makefile
+++ b/Makefile
@@ -1,3 +1,5 @@
+PROJ_DIR := .
+
include Makefile.config
include Makefile.util
include tools/Makefile.tools
@@ -14,7 +16,8 @@ all : design.bin
design.v : design/rom.mem design/*.v
- $(IV) -E $(filter %.v,$^) -DROM_WORDS_COUNT=$(call FILE_LINES,$<) -o $@
+ $(IV) -Iinclude/ -E $(filter %.v,$^) \
+ -DROM_WORDS_COUNT=$(call FILE_LINES,$<) -o $@
design.json : design.v design/rom.mem design/font.mem
$(YOSYS) -p 'read_verilog -defer $<' \
diff --git a/design/stack_machine.v b/design/stack_machine.v
index e6030e4..f68421e 100644
--- a/design/stack_machine.v
+++ b/design/stack_machine.v
@@ -1,5 +1,7 @@
`default_nettype none
+`include "messages.vh"
+
module stack_machine_new
(
/* Those 2 are supposed to be common for both wishbone interfaces */