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-rw-r--r--Makefile5
1 files changed, 4 insertions, 1 deletions
diff --git a/Makefile b/Makefile
index dff217c..39f1f1b 100644
--- a/Makefile
+++ b/Makefile
@@ -1,3 +1,5 @@
+PROJ_DIR := .
+
include Makefile.config
include Makefile.util
include tools/Makefile.tools
@@ -14,7 +16,8 @@ all : design.bin
design.v : design/rom.mem design/*.v
- $(IV) -E $(filter %.v,$^) -DROM_WORDS_COUNT=$(call FILE_LINES,$<) -o $@
+ $(IV) -Iinclude/ -E $(filter %.v,$^) \
+ -DROM_WORDS_COUNT=$(call FILE_LINES,$<) -o $@
design.json : design.v design/rom.mem design/font.mem
$(YOSYS) -p 'read_verilog -defer $<' \