aboutsummaryrefslogtreecommitdiff
path: root/design/interface_wrapper.v
diff options
context:
space:
mode:
authorWojciech Kosior <kwojtus@protonmail.com>2020-12-31 17:59:37 +0100
committerWojciech Kosior <kwojtus@protonmail.com>2020-12-31 17:59:37 +0100
commit96e4965c09bd41f11162120d6312f2aae7efe7ea (patch)
tree4e0a064e4b1bf22b3247bb8c75dc82ec49dc2f8f /design/interface_wrapper.v
parent68c80359ba0983bc21a18c0270025be9b441c0bb (diff)
downloadAGH-engineering-thesis-96e4965c09bd41f11162120d6312f2aae7efe7ea.tar.gz
AGH-engineering-thesis-96e4965c09bd41f11162120d6312f2aae7efe7ea.zip
Add Wishbone datasheets
Diffstat (limited to 'design/interface_wrapper.v')
-rw-r--r--design/interface_wrapper.v8
1 files changed, 6 insertions, 2 deletions
diff --git a/design/interface_wrapper.v b/design/interface_wrapper.v
index ada4a3f..eb708d6 100644
--- a/design/interface_wrapper.v
+++ b/design/interface_wrapper.v
@@ -1,7 +1,11 @@
/*
- * For now, this wrapper ignores SEL_O signals - we'll update it for
- * byte-granular accesses later.
+ * This module transforms a Wishbone pipelined MASTER interface with 32-bit
+ * data port and 8-bit granularity into one with 16-bit data port and 16-bit
+ * granularity. It's just a wrapper, it is not considered a Wishbone SLAVE nor
+ * MASTER by itself (although it could be presented that way). See Wishbone
+ * datasheets of data interfaces in stack_machine.v and wrapped_stack_machine.v.
*/
+
`default_nettype none
module interface_wrapper