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| author | Wojciech Kosior <kwojtus@protonmail.com> | 2020-10-10 16:56:48 +0200 |
|---|---|---|
| committer | Wojciech Kosior <kwojtus@protonmail.com> | 2020-10-10 17:06:58 +0200 |
| commit | 33f05839b7815a5a18a2b920dba4549d2bd7ce16 (patch) | |
| tree | 9ec216c16d2dd520dd9f725900c9ba02b379b6c9 /Makefile | |
| parent | 5e04a9626e2986fc40825d15cb09a274223381e9 (diff) | |
| download | AGH-engineering-thesis-33f05839b7815a5a18a2b920dba4549d2bd7ce16.tar.gz AGH-engineering-thesis-33f05839b7815a5a18a2b920dba4549d2bd7ce16.zip | |
fix yosys synthesis
Diffstat (limited to 'Makefile')
| -rw-r--r-- | Makefile | 5 |
1 files changed, 4 insertions, 1 deletions
@@ -1,3 +1,5 @@ +PROJ_DIR := . + include Makefile.config include Makefile.util include tools/Makefile.tools @@ -14,7 +16,8 @@ all : design.bin design.v : design/rom.mem design/*.v - $(IV) -E $(filter %.v,$^) -DROM_WORDS_COUNT=$(call FILE_LINES,$<) -o $@ + $(IV) -Iinclude/ -E $(filter %.v,$^) \ + -DROM_WORDS_COUNT=$(call FILE_LINES,$<) -o $@ design.json : design.v design/rom.mem design/font.mem $(YOSYS) -p 'read_verilog -defer $<' \ |