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AgeCommit message (Collapse)Author
2020-11-03incorporate SPI module into main designWojciech Kosior
2020-11-03add spi wishbone slave with a simplified flash memory chip model and a test ↵Wojciech Kosior
bench
2020-09-09fix verification when SEL_O != 4'b1111Wojciech Kosior
2020-09-08enable slave and master models to use SEL_ signalWojciech Kosior
2020-09-08remove trailing whitespaceWojciech Kosior
2020-09-05replace fixed-width constant from now-parameterized wb slave modelWojciech Kosior
2020-09-04fix master after parametrizationWojciech Kosior
2020-09-04enable parametrizable address and data widths for master modelWojciech Kosior
2020-09-04enable parametrizable address and data widths for slave modelWojciech Kosior
2020-09-02remove unnecessary complexity from preprocessor error throwingWojciech Kosior
2020-09-02add bench for wishbone sram wrapperWojciech Kosior
2020-09-01fix line counting in test model (avoid having picture shifted 1 line down on ↵Wojciech Kosior
virtual display)
2020-09-01start anewWojciech Kosior
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