| Age | Commit message (Expand) | Author |
|---|---|---|
| 2020-12-31 | Add Wishbone datasheets | Wojciech Kosior |
| 2020-09-09 | fix verification when SEL_O != 4'b1111 | Wojciech Kosior |
| 2020-09-08 | enable slave and master models to use SEL_ signal | Wojciech Kosior |
| 2020-09-08 | remove trailing whitespace | Wojciech Kosior |
| 2020-09-04 | fix master after parametrization | Wojciech Kosior |
| 2020-09-04 | enable parametrizable address and data widths for master model | Wojciech Kosior |
| 2020-09-02 | remove unnecessary complexity from preprocessor error throwing | Wojciech Kosior |
| 2020-09-01 | start anew | Wojciech Kosior |
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index : AGH-engineering-thesis | |
| code related to my engineering thesis at AGH University of Science and Technology in Kraków, Poland | Gitolite3 |
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