diff options
Diffstat (limited to 'tests/intercon/test.v')
| -rw-r--r-- | tests/intercon/test.v | 90 |
1 files changed, 78 insertions, 12 deletions
diff --git a/tests/intercon/test.v b/tests/intercon/test.v index f2102a6..721502c 100644 --- a/tests/intercon/test.v +++ b/tests/intercon/test.v @@ -31,16 +31,26 @@ module intercon_test(); wire M0_WE_O, M1_WE_O; wire M0_STALL_I, M1_STALL_I; - wire S0_ACK_O, S1_ACK_O, S2_ACK_O, S3_ACK_O; - wire S0_CLK_I, S1_CLK_I, S2_CLK_I, S3_CLK_I; - wire [17:0] S0_ADR_I, S1_ADR_I, S2_ADR_I, S3_ADR_I; - wire [15:0] S0_DAT_I, S1_DAT_I, S2_DAT_I, S3_DAT_I; - wire [15:0] S0_DAT_O, S1_DAT_O, S2_DAT_O, S3_DAT_O; - wire S0_SEL_I, S1_SEL_I, S2_SEL_I, S3_SEL_I; /* Always high */ - wire S0_RST_I, S1_RST_I, S2_RST_I, S3_RST_I; - wire S0_STB_I, S1_STB_I, S2_STB_I, S3_STB_I; - wire S0_WE_I, S1_WE_I, S2_WE_I, S3_WE_I; - wire S0_STALL_O, S1_STALL_O, S2_STALL_O, S3_STALL_O; + wire S0_ACK_O, S1_ACK_O, S2_ACK_O, + S3_ACK_O, S4_ACK_O, S5_ACK_O; + wire S0_CLK_I, S1_CLK_I, S2_CLK_I, + S3_CLK_I, S4_CLK_I, S5_CLK_I; + wire [17:0] S0_ADR_I, S1_ADR_I; + wire [16:0] S2_ADR_I, S3_ADR_I, S4_ADR_I, S5_ADR_I; + wire [15:0] S0_DAT_I, S1_DAT_I, S2_DAT_I, + S3_DAT_I, S4_DAT_I, S5_DAT_I; + wire [15:0] S0_DAT_O, S1_DAT_O, S2_DAT_O, + S3_DAT_O, S4_DAT_O, S5_DAT_O; + wire S0_SEL_I, S1_SEL_I, S2_SEL_I, + S3_SEL_I, S4_SEL_I, S5_SEL_I; /* Always high */ + wire S0_RST_I, S1_RST_I, S2_RST_I, + S3_RST_I, S4_RST_I, S5_RST_I; + wire S0_STB_I, S1_STB_I, S2_STB_I, + S3_STB_I, S4_STB_I, S5_STB_I; + wire S0_WE_I, S1_WE_I, S2_WE_I, + S3_WE_I, S4_WE_I, S5_WE_I; + wire S0_STALL_O, S1_STALL_O, S2_STALL_O, + S3_STALL_O, S4_STALL_O, S5_STALL_O; /* Non-wishbone */ wire M0_finished; @@ -130,7 +140,8 @@ module intercon_test(); memory_slave_model #( - .SLAVE_NR(2) + .SLAVE_NR(2), + .ADR_BITS(17) ) slave2 ( .ACK_O(S2_ACK_O), @@ -147,7 +158,8 @@ module intercon_test(); memory_slave_model #( - .SLAVE_NR(3) + .SLAVE_NR(3), + .ADR_BITS(17) ) slave3 ( .ACK_O(S3_ACK_O), @@ -162,6 +174,42 @@ module intercon_test(); .STALL_O(S3_STALL_O) ); + memory_slave_model + #( + .SLAVE_NR(4), + .ADR_BITS(17) + ) slave4 + ( + .ACK_O(S4_ACK_O), + .CLK_I(CLK), + .ADR_I(S4_ADR_I), + .DAT_I(S4_DAT_I), + .DAT_O(S4_DAT_O), + .SEL_I(S4_SEL_I), + .RST_I(RST), + .STB_I(S4_STB_I), + .WE_I(S4_WE_I), + .STALL_O(S4_STALL_O) + ); + + memory_slave_model + #( + .SLAVE_NR(5), + .ADR_BITS(17) + ) slave5 + ( + .ACK_O(S5_ACK_O), + .CLK_I(CLK), + .ADR_I(S5_ADR_I), + .DAT_I(S5_DAT_I), + .DAT_O(S5_DAT_O), + .SEL_I(S5_SEL_I), + .RST_I(RST), + .STB_I(S5_STB_I), + .WE_I(S5_WE_I), + .STALL_O(S5_STALL_O) + ); + intercon intercon ( .CLK(CLK), @@ -199,6 +247,22 @@ module intercon_test(); .S3_WE_I(S3_WE_I), .S3_STALL_O(S3_STALL_O), + .S4_ACK_O(S4_ACK_O), + .S4_ADR_I(S4_ADR_I), + .S4_DAT_I(S4_DAT_I), + .S4_DAT_O(S4_DAT_O), + .S4_STB_I(S4_STB_I), + .S4_WE_I(S4_WE_I), + .S4_STALL_O(S4_STALL_O), + + .S5_ACK_O(S5_ACK_O), + .S5_ADR_I(S5_ADR_I), + .S5_DAT_I(S5_DAT_I), + .S5_DAT_O(S5_DAT_O), + .S5_STB_I(S5_STB_I), + .S5_WE_I(S5_WE_I), + .S5_STALL_O(S5_STALL_O), + .M0_ACK_I(M0_ACK_I), .M0_ADR_O(M0_ADR_O), .M0_DAT_I(M0_DAT_I), @@ -222,6 +286,8 @@ module intercon_test(); assign S1_SEL_I = 1; assign S2_SEL_I = 1; assign S3_SEL_I = 1; + assign S4_SEL_I = 1; + assign S5_SEL_I = 1; integer i; |