diff options
| -rw-r--r-- | design/intercon.v | 36 | ||||
| -rw-r--r-- | design/slave_dispatcher.v | 59 | ||||
| -rw-r--r-- | design/soc.v | 69 | ||||
| -rw-r--r-- | tests/intercon/test.v | 90 | ||||
| -rw-r--r-- | tests/slave_dispatcher/operations.memv | 28 | ||||
| -rw-r--r-- | tests/slave_dispatcher/test.v | 90 |
6 files changed, 309 insertions, 63 deletions
diff --git a/design/intercon.v b/design/intercon.v index 926414d..9948735 100644 --- a/design/intercon.v +++ b/design/intercon.v @@ -23,7 +23,7 @@ module intercon input wire S1_STALL_O, input wire S2_ACK_O, - output wire [17:0] S2_ADR_I, + output wire [16:0] S2_ADR_I, output wire [15:0] S2_DAT_I, input wire [15:0] S2_DAT_O, output wire S2_STB_I, @@ -31,13 +31,29 @@ module intercon input wire S2_STALL_O, input wire S3_ACK_O, - output wire [17:0] S3_ADR_I, + output wire [16:0] S3_ADR_I, output wire [15:0] S3_DAT_I, input wire [15:0] S3_DAT_O, output wire S3_STB_I, output wire S3_WE_I, input wire S3_STALL_O, + input wire S4_ACK_O, + output wire [16:0] S4_ADR_I, + output wire [15:0] S4_DAT_I, + input wire [15:0] S4_DAT_O, + output wire S4_STB_I, + output wire S4_WE_I, + input wire S4_STALL_O, + + input wire S5_ACK_O, + output wire [16:0] S5_ADR_I, + output wire [15:0] S5_DAT_I, + input wire [15:0] S5_DAT_O, + output wire S5_STB_I, + output wire S5_WE_I, + input wire S5_STALL_O, + output wire M0_ACK_I, input wire [19:0] M0_ADR_O, output wire [15:0] M0_DAT_I, @@ -111,6 +127,22 @@ module intercon .S3_WE_I(S3_WE_I), .S3_STALL_O(S3_STALL_O), + .S4_ACK_O(S4_ACK_O), + .S4_ADR_I(S4_ADR_I), + .S4_DAT_I(S4_DAT_I), + .S4_DAT_O(S4_DAT_O), + .S4_STB_I(S4_STB_I), + .S4_WE_I(S4_WE_I), + .S4_STALL_O(S4_STALL_O), + + .S5_ACK_O(S5_ACK_O), + .S5_ADR_I(S5_ADR_I), + .S5_DAT_I(S5_DAT_I), + .S5_DAT_O(S5_DAT_O), + .S5_STB_I(S5_STB_I), + .S5_WE_I(S5_WE_I), + .S5_STALL_O(S5_STALL_O), + .S_COMBINED_ACK_O(S_COMBINED_ACK_O), .S_COMBINED_ADR_I(S_COMBINED_ADR_I), .S_COMBINED_DAT_I(S_COMBINED_DAT_I), diff --git a/design/slave_dispatcher.v b/design/slave_dispatcher.v index 6377a57..4da0dbd 100644 --- a/design/slave_dispatcher.v +++ b/design/slave_dispatcher.v @@ -22,7 +22,7 @@ module slave_dispatcher input wire S1_STALL_O, input wire S2_ACK_O, - output wire [17:0] S2_ADR_I, + output wire [16:0] S2_ADR_I, output wire [15:0] S2_DAT_I, input wire [15:0] S2_DAT_O, output wire S2_STB_I, @@ -30,13 +30,29 @@ module slave_dispatcher input wire S2_STALL_O, input wire S3_ACK_O, - output wire [17:0] S3_ADR_I, + output wire [16:0] S3_ADR_I, output wire [15:0] S3_DAT_I, input wire [15:0] S3_DAT_O, output wire S3_STB_I, output wire S3_WE_I, input wire S3_STALL_O, + input wire S4_ACK_O, + output wire [16:0] S4_ADR_I, + output wire [15:0] S4_DAT_I, + input wire [15:0] S4_DAT_O, + output wire S4_STB_I, + output wire S4_WE_I, + input wire S4_STALL_O, + + input wire S5_ACK_O, + output wire [16:0] S5_ADR_I, + output wire [15:0] S5_DAT_I, + input wire [15:0] S5_DAT_O, + output wire S5_STB_I, + output wire S5_WE_I, + input wire S5_STALL_O, + output wire S_COMBINED_ACK_O, input wire [19:0] S_COMBINED_ADR_I, input wire [15:0] S_COMBINED_DAT_I, @@ -46,29 +62,38 @@ module slave_dispatcher output wire S_COMBINED_STALL_O ); - wire [0:3] acks; - wire [0:3] stalls; - wire [15:0] datas [0:3]; - assign acks = {S0_ACK_O, S1_ACK_O, S2_ACK_O, S3_ACK_O}; - assign stalls = {S0_STALL_O, S1_STALL_O, S2_STALL_O, S3_STALL_O}; + wire [0:5] acks; + wire [0:5] stalls; + wire [15:0] datas [0:5]; + assign acks = {S0_ACK_O, S1_ACK_O, S2_ACK_O, S3_ACK_O, S4_ACK_O, S5_ACK_O}; + assign stalls = {S0_STALL_O, S1_STALL_O, S2_STALL_O, + S3_STALL_O, S4_STALL_O, S5_STALL_O}; assign datas[0] = S0_DAT_O; assign datas[1] = S1_DAT_O; assign datas[2] = S2_DAT_O; assign datas[3] = S3_DAT_O; + assign datas[4] = S4_DAT_O; + assign datas[5] = S5_DAT_O; reg [1:0] commands_awaiting; - reg [1:0] slave_last_accessed; + reg [2:0] slave_last_accessed; wire working; - wire [1:0] slave_accessed; + wire [2:0] slave_accessed; + wire [2:0] slave_requested; wire slave_switch; wire [1:0] commands_awaiting_next_tick; assign working = commands_awaiting || S_COMBINED_STB_I; + assign slave_requested = S_COMBINED_ADR_I[19] ? + /* one of 4 smaller slaves */ + S_COMBINED_ADR_I[18:17] + 2 : + /* one of 2 bigger slaves */ + S_COMBINED_ADR_I[19:18]; assign slave_accessed = commands_awaiting ? slave_last_accessed : - S_COMBINED_ADR_I[19:18]; + slave_requested; assign S_COMBINED_ACK_O = acks[slave_accessed] && working; assign S_COMBINED_DAT_O = datas[slave_accessed]; - assign slave_switch = slave_accessed != S_COMBINED_ADR_I[19:18]; + assign slave_switch = slave_accessed != slave_requested; assign S_COMBINED_STALL_O = stalls[slave_accessed] || slave_switch || (commands_awaiting == 3 && !S_COMBINED_ACK_O); assign commands_awaiting_next_tick @@ -94,13 +119,17 @@ module slave_dispatcher assign S0_ADR_I = S_COMBINED_ADR_I[17:0]; assign S1_ADR_I = S_COMBINED_ADR_I[17:0]; - assign S2_ADR_I = S_COMBINED_ADR_I[17:0]; - assign S3_ADR_I = S_COMBINED_ADR_I[17:0]; + assign S2_ADR_I = S_COMBINED_ADR_I[16:0]; + assign S3_ADR_I = S_COMBINED_ADR_I[16:0]; + assign S4_ADR_I = S_COMBINED_ADR_I[16:0]; + assign S5_ADR_I = S_COMBINED_ADR_I[16:0]; assign S0_DAT_I = S_COMBINED_DAT_I; assign S1_DAT_I = S_COMBINED_DAT_I; assign S2_DAT_I = S_COMBINED_DAT_I; assign S3_DAT_I = S_COMBINED_DAT_I; + assign S4_DAT_I = S_COMBINED_DAT_I; + assign S5_DAT_I = S_COMBINED_DAT_I; wire pass_strobe; assign pass_strobe = S_COMBINED_STB_I && !slave_switch && @@ -110,9 +139,13 @@ module slave_dispatcher assign S1_STB_I = slave_accessed == 1 && pass_strobe; assign S2_STB_I = slave_accessed == 2 && pass_strobe; assign S3_STB_I = slave_accessed == 3 && pass_strobe; + assign S4_STB_I = slave_accessed == 4 && pass_strobe; + assign S5_STB_I = slave_accessed == 5 && pass_strobe; assign S0_WE_I = S_COMBINED_WE_I; assign S1_WE_I = S_COMBINED_WE_I; assign S2_WE_I = S_COMBINED_WE_I; assign S3_WE_I = S_COMBINED_WE_I; + assign S4_WE_I = S_COMBINED_WE_I; + assign S5_WE_I = S_COMBINED_WE_I; endmodule // slave_dispatcher diff --git a/design/soc.v b/design/soc.v index c7312f3..b395404 100644 --- a/design/soc.v +++ b/design/soc.v @@ -4,6 +4,9 @@ * slave 0 - embedded RAM (256x16) with memory initialized from file * slave 1 - SRAM * slave 2 - VGA text-mode controller + * slave 3 - SPI master controller + * slave 4 - UART controller (yet to be added) + * slave 5 - miscellaneous registers (yet to be added) * * The memory map from stack machine's viewpoint is as follows: * h000000 - h0001FF - embedded RAM @@ -12,13 +15,16 @@ * h100000 - h1009FF - VGA text memory * h100A00 - h100A01 - VGA power-on register * h100A02 - h100FFF - undefined (actually, repetitions of VGA power-on reg) - * h101000 - h17FFFF - undefined (actually, repetitions of VGA memory) - * h180000 - h1801FF - SPI data transfer memory - * h180200 - h180201 - SPI bytes_to_output reg - * h180202 - h180203 - SPI bytes_to_receive reg - * h180204 - h180207 - SPI operating reg - * h180208 - h1803FF - undefined (actually, repetitions of SPI regs) - * h180400 - h1FFFFF - undefined (actually, repetitions of SPI memory) + * h101000 - h13FFFF - undefined (actually, repetitions of VGA memory & regs) + * h140000 - h1401FF - SPI data transfer memory + * h140200 - h140201 - SPI bytes_to_output reg + * h140202 - h140203 - SPI bytes_to_receive reg + * h140204 - h140207 - SPI operating reg + * h140204 - h140207 - SPI operating reg + * h140208 - h1403FF - undefined (actually, repetitions of SPI regs) + * h140400 - h17FFFF - undefined (actually, repetitions of SPI memory & regs) + * h180000 - h1BFFFF - UART (not implemented yet) + * h1C0000 - h1FFFFF - miscellaneous peripherals (not implemented yet) */ `default_nettype none @@ -73,13 +79,20 @@ module soc wire M0_WE_O, M1_WE_O; wire M0_STALL_I, M1_STALL_I; - wire S0_ACK_O, S1_ACK_O, S2_ACK_O, S3_ACK_O; - wire [17:0] S0_ADR_I, S1_ADR_I, S2_ADR_I, S3_ADR_I; - wire [15:0] S0_DAT_I, S1_DAT_I, S2_DAT_I, S3_DAT_I; - wire [15:0] S0_DAT_O, S1_DAT_O, S2_DAT_O, S3_DAT_O; - wire S0_STB_I, S1_STB_I, S2_STB_I, S3_STB_I; - wire S0_WE_I, S1_WE_I, S2_WE_I, S3_WE_I; - wire S0_STALL_O, S1_STALL_O, S2_STALL_O, S3_STALL_O; + wire S0_ACK_O, S1_ACK_O, S2_ACK_O, + S3_ACK_O, S4_ACK_O, S5_ACK_O; + wire [17:0] S0_ADR_I, S1_ADR_I; + wire [16:0] S2_ADR_I, S3_ADR_I, S4_ADR_I, S5_ADR_I; + wire [15:0] S0_DAT_I, S1_DAT_I, S2_DAT_I, + S3_DAT_I, S4_DAT_I, S5_DAT_I; + wire [15:0] S0_DAT_O, S1_DAT_O, S2_DAT_O, + S3_DAT_O, S4_DAT_O, S5_DAT_O; + wire S0_STB_I, S1_STB_I, S2_STB_I, + S3_STB_I, S4_STB_I, S5_STB_I; + wire S0_WE_I, S1_WE_I, S2_WE_I, + S3_WE_I, S4_WE_I, S5_WE_I; + wire S0_STALL_O, S1_STALL_O, S2_STALL_O, + S3_STALL_O, S4_STALL_O, S5_STALL_O; wire CLK; wire RST; @@ -200,6 +213,18 @@ module soc .ss_n(spi_ss_n) ); + /* + * Slaves 4 and 5 will be UART controller and miscellaneous registers, + * but for now - they're omitted + */ + assign S4_ACK_O = 1; + assign S4_DAT_O = 0; + assign S4_STALL_O = 0; + + assign S5_ACK_O = 1; + assign S5_DAT_O = 0; + assign S5_STALL_O = 0; + intercon intercon ( .CLK(CLK), @@ -237,6 +262,22 @@ module soc .S3_WE_I(S3_WE_I), .S3_STALL_O(S3_STALL_O), + .S4_ACK_O(S4_ACK_O), + .S4_ADR_I(S4_ADR_I), + .S4_DAT_I(S4_DAT_I), + .S4_DAT_O(S4_DAT_O), + .S4_STB_I(S4_STB_I), + .S4_WE_I(S4_WE_I), + .S4_STALL_O(S4_STALL_O), + + .S5_ACK_O(S5_ACK_O), + .S5_ADR_I(S5_ADR_I), + .S5_DAT_I(S5_DAT_I), + .S5_DAT_O(S5_DAT_O), + .S5_STB_I(S5_STB_I), + .S5_WE_I(S5_WE_I), + .S5_STALL_O(S5_STALL_O), + .M0_ACK_I(M0_ACK_I), .M0_ADR_O(M0_ADR_O), .M0_DAT_I(M0_DAT_I), diff --git a/tests/intercon/test.v b/tests/intercon/test.v index f2102a6..721502c 100644 --- a/tests/intercon/test.v +++ b/tests/intercon/test.v @@ -31,16 +31,26 @@ module intercon_test(); wire M0_WE_O, M1_WE_O; wire M0_STALL_I, M1_STALL_I; - wire S0_ACK_O, S1_ACK_O, S2_ACK_O, S3_ACK_O; - wire S0_CLK_I, S1_CLK_I, S2_CLK_I, S3_CLK_I; - wire [17:0] S0_ADR_I, S1_ADR_I, S2_ADR_I, S3_ADR_I; - wire [15:0] S0_DAT_I, S1_DAT_I, S2_DAT_I, S3_DAT_I; - wire [15:0] S0_DAT_O, S1_DAT_O, S2_DAT_O, S3_DAT_O; - wire S0_SEL_I, S1_SEL_I, S2_SEL_I, S3_SEL_I; /* Always high */ - wire S0_RST_I, S1_RST_I, S2_RST_I, S3_RST_I; - wire S0_STB_I, S1_STB_I, S2_STB_I, S3_STB_I; - wire S0_WE_I, S1_WE_I, S2_WE_I, S3_WE_I; - wire S0_STALL_O, S1_STALL_O, S2_STALL_O, S3_STALL_O; + wire S0_ACK_O, S1_ACK_O, S2_ACK_O, + S3_ACK_O, S4_ACK_O, S5_ACK_O; + wire S0_CLK_I, S1_CLK_I, S2_CLK_I, + S3_CLK_I, S4_CLK_I, S5_CLK_I; + wire [17:0] S0_ADR_I, S1_ADR_I; + wire [16:0] S2_ADR_I, S3_ADR_I, S4_ADR_I, S5_ADR_I; + wire [15:0] S0_DAT_I, S1_DAT_I, S2_DAT_I, + S3_DAT_I, S4_DAT_I, S5_DAT_I; + wire [15:0] S0_DAT_O, S1_DAT_O, S2_DAT_O, + S3_DAT_O, S4_DAT_O, S5_DAT_O; + wire S0_SEL_I, S1_SEL_I, S2_SEL_I, + S3_SEL_I, S4_SEL_I, S5_SEL_I; /* Always high */ + wire S0_RST_I, S1_RST_I, S2_RST_I, + S3_RST_I, S4_RST_I, S5_RST_I; + wire S0_STB_I, S1_STB_I, S2_STB_I, + S3_STB_I, S4_STB_I, S5_STB_I; + wire S0_WE_I, S1_WE_I, S2_WE_I, + S3_WE_I, S4_WE_I, S5_WE_I; + wire S0_STALL_O, S1_STALL_O, S2_STALL_O, + S3_STALL_O, S4_STALL_O, S5_STALL_O; /* Non-wishbone */ wire M0_finished; @@ -130,7 +140,8 @@ module intercon_test(); memory_slave_model #( - .SLAVE_NR(2) + .SLAVE_NR(2), + .ADR_BITS(17) ) slave2 ( .ACK_O(S2_ACK_O), @@ -147,7 +158,8 @@ module intercon_test(); memory_slave_model #( - .SLAVE_NR(3) + .SLAVE_NR(3), + .ADR_BITS(17) ) slave3 ( .ACK_O(S3_ACK_O), @@ -162,6 +174,42 @@ module intercon_test(); .STALL_O(S3_STALL_O) ); + memory_slave_model + #( + .SLAVE_NR(4), + .ADR_BITS(17) + ) slave4 + ( + .ACK_O(S4_ACK_O), + .CLK_I(CLK), + .ADR_I(S4_ADR_I), + .DAT_I(S4_DAT_I), + .DAT_O(S4_DAT_O), + .SEL_I(S4_SEL_I), + .RST_I(RST), + .STB_I(S4_STB_I), + .WE_I(S4_WE_I), + .STALL_O(S4_STALL_O) + ); + + memory_slave_model + #( + .SLAVE_NR(5), + .ADR_BITS(17) + ) slave5 + ( + .ACK_O(S5_ACK_O), + .CLK_I(CLK), + .ADR_I(S5_ADR_I), + .DAT_I(S5_DAT_I), + .DAT_O(S5_DAT_O), + .SEL_I(S5_SEL_I), + .RST_I(RST), + .STB_I(S5_STB_I), + .WE_I(S5_WE_I), + .STALL_O(S5_STALL_O) + ); + intercon intercon ( .CLK(CLK), @@ -199,6 +247,22 @@ module intercon_test(); .S3_WE_I(S3_WE_I), .S3_STALL_O(S3_STALL_O), + .S4_ACK_O(S4_ACK_O), + .S4_ADR_I(S4_ADR_I), + .S4_DAT_I(S4_DAT_I), + .S4_DAT_O(S4_DAT_O), + .S4_STB_I(S4_STB_I), + .S4_WE_I(S4_WE_I), + .S4_STALL_O(S4_STALL_O), + + .S5_ACK_O(S5_ACK_O), + .S5_ADR_I(S5_ADR_I), + .S5_DAT_I(S5_DAT_I), + .S5_DAT_O(S5_DAT_O), + .S5_STB_I(S5_STB_I), + .S5_WE_I(S5_WE_I), + .S5_STALL_O(S5_STALL_O), + .M0_ACK_I(M0_ACK_I), .M0_ADR_O(M0_ADR_O), .M0_DAT_I(M0_DAT_I), @@ -222,6 +286,8 @@ module intercon_test(); assign S1_SEL_I = 1; assign S2_SEL_I = 1; assign S3_SEL_I = 1; + assign S4_SEL_I = 1; + assign S5_SEL_I = 1; integer i; diff --git a/tests/slave_dispatcher/operations.memv b/tests/slave_dispatcher/operations.memv index 8785d5c..ab534f6 100644 --- a/tests/slave_dispatcher/operations.memv +++ b/tests/slave_dispatcher/operations.memv @@ -1,6 +1,6 @@ `include "macroasm.vh" // look into macroasm.vh for more info -// The beginning copied from self test, only 1st slave is being accessed. +// The beginning copied from self test, only slave 0 is being accessed. `WRITE(00000, abcd) `WAIT `READ (00000, abcd) @@ -29,35 +29,43 @@ `WRITE(40040, efef) `WRITE(80002, 1f1f) `WRITE(c00c0, 1d1d) +`WRITE(a0002, aaea) +`WRITE(e00c0, cc4d) `READ (80002, 1f1f) `READ (c00c0, 1d1d) `READ (40040, efef) +`READ (a0002, aaea) +`READ (e00c0, cc4d) `WAIT `WAIT -// Make a sequence of commands to slave 3 (addresses c0000 - fffff) +// Make a sequence of commands to slave 4 (addresses c0000 - dffff) `READ (c00c0, 1d1d) `WRITE(c1111, 0022) `READ (c00c0, 1d1d) +`WRITE(c00c0, 0111) `WRITE(c0001, 0001) `WRITE(c0002, 0002) `READ (c0001, 0001) `READ (c0002, 0002) `READ (c0001, 0001) +`READ (c00c0, 0111) `WRITE(c0003, 0003) `WRITE(c0002, 2222) `READ (c0002, 2222) `READ (c0003, 0003) -`WRITE(fffff, 5555) +`WRITE(dffff, 5555) `READ (c1111, 0022) -// Put a single command to another slave in-between commands to slave 3 +// Put a single command to another slave in-between commands to slave 4 `WRITE(4ffff, b6b6) -`READ (fffff, 5555) -`WRITE(eeeee, aaaa) -`READ (eeeee, aaaa) -// Let slave 3 take a breath now +`READ (dffff, 5555) +`WRITE(deeee, aaaa) +`READ (deeee, aaaa) +// Let slave 4 take a breath now `READ (4ffff, b6b6) `DESELECT -// We made writes to c0002 and c0001, make sure corresponding addreses -// in other slaves were not overwritten by mistake +// We made writes to c0002, c0001 and c00c0, make sure corresponding +// addreses in other slaves were not overwritten by mistake `READ (80002, 1f1f) +`READ (a0002, aaea) `READ (00001, 4321) +`READ (e00c0, cc4d) diff --git a/tests/slave_dispatcher/test.v b/tests/slave_dispatcher/test.v index 49c03ef..ad85b1f 100644 --- a/tests/slave_dispatcher/test.v +++ b/tests/slave_dispatcher/test.v @@ -26,16 +26,26 @@ module slave_dispatcher_test(); wire M_WE_O; wire M_STALL_I; - wire S0_ACK_O, S1_ACK_O, S2_ACK_O, S3_ACK_O; - wire S0_CLK_I, S1_CLK_I, S2_CLK_I, S3_CLK_I; - wire [17:0] S0_ADR_I, S1_ADR_I, S2_ADR_I, S3_ADR_I; - wire [15:0] S0_DAT_I, S1_DAT_I, S2_DAT_I, S3_DAT_I; - wire [15:0] S0_DAT_O, S1_DAT_O, S2_DAT_O, S3_DAT_O; - wire S0_SEL_I, S1_SEL_I, S2_SEL_I, S3_SEL_I; /* Always high */ - wire S0_RST_I, S1_RST_I, S2_RST_I, S3_RST_I; - wire S0_STB_I, S1_STB_I, S2_STB_I, S3_STB_I; - wire S0_WE_I, S1_WE_I, S2_WE_I, S3_WE_I; - wire S0_STALL_O, S1_STALL_O, S2_STALL_O, S3_STALL_O; + wire S0_ACK_O, S1_ACK_O, S2_ACK_O, + S3_ACK_O, S4_ACK_O, S5_ACK_O; + wire S0_CLK_I, S1_CLK_I, S2_CLK_I, + S3_CLK_I, S4_CLK_I, S5_CLK_I; + wire [17:0] S0_ADR_I, S1_ADR_I; + wire [16:0] S2_ADR_I, S3_ADR_I, S4_ADR_I, S5_ADR_I; + wire [15:0] S0_DAT_I, S1_DAT_I, S2_DAT_I, + S3_DAT_I, S4_DAT_I, S5_DAT_I; + wire [15:0] S0_DAT_O, S1_DAT_O, S2_DAT_O, + S3_DAT_O, S4_DAT_O, S5_DAT_O; + wire S0_SEL_I, S1_SEL_I, S2_SEL_I, + S3_SEL_I, S4_SEL_I, S5_SEL_I; /* Always high */ + wire S0_RST_I, S1_RST_I, S2_RST_I, + S3_RST_I, S4_RST_I, S5_RST_I; + wire S0_STB_I, S1_STB_I, S2_STB_I, + S3_STB_I, S4_STB_I, S5_STB_I; + wire S0_WE_I, S1_WE_I, S2_WE_I, + S3_WE_I, S4_WE_I, S5_WE_I; + wire S0_STALL_O, S1_STALL_O, S2_STALL_O, + S3_STALL_O, S4_STALL_O, S5_STALL_O; wire S_COMBINED_ACK_O; wire [19:0] S_COMBINED_ADR_I; @@ -105,7 +115,8 @@ module slave_dispatcher_test(); memory_slave_model #( - .SLAVE_NR(2) + .SLAVE_NR(2), + .ADR_BITS(17) ) slave2 ( .ACK_O(S2_ACK_O), @@ -122,7 +133,8 @@ module slave_dispatcher_test(); memory_slave_model #( - .SLAVE_NR(3) + .SLAVE_NR(3), + .ADR_BITS(17) ) slave3 ( .ACK_O(S3_ACK_O), @@ -137,6 +149,42 @@ module slave_dispatcher_test(); .STALL_O(S3_STALL_O) ); + memory_slave_model + #( + .SLAVE_NR(4), + .ADR_BITS(17) + ) slave4 + ( + .ACK_O(S4_ACK_O), + .CLK_I(CLK), + .ADR_I(S4_ADR_I), + .DAT_I(S4_DAT_I), + .DAT_O(S4_DAT_O), + .SEL_I(S4_SEL_I), + .RST_I(RST), + .STB_I(S4_STB_I), + .WE_I(S4_WE_I), + .STALL_O(S4_STALL_O) + ); + + memory_slave_model + #( + .SLAVE_NR(3), + .ADR_BITS(17) + ) slave5 + ( + .ACK_O(S5_ACK_O), + .CLK_I(CLK), + .ADR_I(S5_ADR_I), + .DAT_I(S5_DAT_I), + .DAT_O(S5_DAT_O), + .SEL_I(S5_SEL_I), + .RST_I(RST), + .STB_I(S5_STB_I), + .WE_I(S5_WE_I), + .STALL_O(S5_STALL_O) + ); + slave_dispatcher dispatcher ( .CLK(CLK), @@ -174,6 +222,22 @@ module slave_dispatcher_test(); .S3_WE_I(S3_WE_I), .S3_STALL_O(S3_STALL_O), + .S4_ACK_O(S4_ACK_O), + .S4_ADR_I(S4_ADR_I), + .S4_DAT_I(S4_DAT_I), + .S4_DAT_O(S4_DAT_O), + .S4_STB_I(S4_STB_I), + .S4_WE_I(S4_WE_I), + .S4_STALL_O(S4_STALL_O), + + .S5_ACK_O(S5_ACK_O), + .S5_ADR_I(S5_ADR_I), + .S5_DAT_I(S5_DAT_I), + .S5_DAT_O(S5_DAT_O), + .S5_STB_I(S5_STB_I), + .S5_WE_I(S5_WE_I), + .S5_STALL_O(S5_STALL_O), + .S_COMBINED_ACK_O(S_COMBINED_ACK_O), .S_COMBINED_ADR_I(S_COMBINED_ADR_I), .S_COMBINED_DAT_I(S_COMBINED_DAT_I), @@ -196,6 +260,8 @@ module slave_dispatcher_test(); assign S1_SEL_I = 1; assign S2_SEL_I = 1; assign S3_SEL_I = 1; + assign S4_SEL_I = 1; + assign S5_SEL_I = 1; integer i; |