diff options
Diffstat (limited to 'tests/embedded_bram_slave')
| -rw-r--r-- | tests/embedded_bram_slave/operations.memv | 36 | ||||
| -rw-r--r-- | tests/embedded_bram_slave/rom.mem | 259 | ||||
| -rw-r--r-- | tests/embedded_bram_slave/test.v | 121 |
3 files changed, 416 insertions, 0 deletions
diff --git a/tests/embedded_bram_slave/operations.memv b/tests/embedded_bram_slave/operations.memv new file mode 100644 index 0000000..9cca800 --- /dev/null +++ b/tests/embedded_bram_slave/operations.memv @@ -0,0 +1,36 @@ +`include "macroasm.vh" // look into macroasm.vh for more info + +// First, check if memory initialization went ok +`READ (00000, 0000) // 0*7 at address 0 +`DESELECT +`READ (00001, 0007) // 1*7 at address 1 +`READ (00002, 000E) // 2*7 at address 2 +`WAIT +`WAIT +`READ (00089, 03BF) // 137*7 at address 137 +`READ (00101, 0707) // 257*7 at address 257 + +// Now, check that writing works (this is based on self test) +`WRITE(00000, abcd) +`WAIT +`READ (00000, abcd) +`WRITE(00001, 1234) +`READ (00000, abcd) +`DESELECT +`DESELECT +`READ (00001, 1234) +`WRITE(001E0, a2a2) +`WRITE(00001, 4321) +`READ (001E0, a2a2) +`WAIT +`WAIT +`WAIT +`WAIT +`WAIT +`DESELECT +`DESELECT +`DESELECT +`WAIT +`DESELECT +`WAIT +`READ(00001, 4321) diff --git a/tests/embedded_bram_slave/rom.mem b/tests/embedded_bram_slave/rom.mem new file mode 100644 index 0000000..a200d81 --- /dev/null +++ b/tests/embedded_bram_slave/rom.mem @@ -0,0 +1,259 @@ +// numbers 0, 7, 2*7, 3*7, ..., 257*7 in binary +0000000000000000 +0000000000000111 +0000000000001110 +0000000000010101 +0000000000011100 +0000000000100011 +0000000000101010 +0000000000110001 +0000000000111000 +0000000000111111 +0000000001000110 +0000000001001101 +0000000001010100 +0000000001011011 +0000000001100010 +0000000001101001 +0000000001110000 +0000000001110111 +0000000001111110 +0000000010000101 +0000000010001100 +0000000010010011 +0000000010011010 +0000000010100001 +0000000010101000 +0000000010101111 +0000000010110110 +0000000010111101 +0000000011000100 +0000000011001011 +0000000011010010 +0000000011011001 +0000000011100000 +0000000011100111 +0000000011101110 +0000000011110101 +0000000011111100 +0000000100000011 +0000000100001010 +0000000100010001 +0000000100011000 +0000000100011111 +0000000100100110 +0000000100101101 +0000000100110100 +0000000100111011 +0000000101000010 +0000000101001001 +0000000101010000 +0000000101010111 +0000000101011110 +0000000101100101 +0000000101101100 +0000000101110011 +0000000101111010 +0000000110000001 +0000000110001000 +0000000110001111 +0000000110010110 +0000000110011101 +0000000110100100 +0000000110101011 +0000000110110010 +0000000110111001 +0000000111000000 +0000000111000111 +0000000111001110 +0000000111010101 +0000000111011100 +0000000111100011 +0000000111101010 +0000000111110001 +0000000111111000 +0000000111111111 +0000001000000110 +0000001000001101 +0000001000010100 +0000001000011011 +0000001000100010 +0000001000101001 +0000001000110000 +0000001000110111 +0000001000111110 +0000001001000101 +0000001001001100 +0000001001010011 +0000001001011010 +0000001001100001 +0000001001101000 +0000001001101111 +0000001001110110 +0000001001111101 +0000001010000100 +0000001010001011 +0000001010010010 +0000001010011001 +0000001010100000 +0000001010100111 +0000001010101110 +0000001010110101 +0000001010111100 +0000001011000011 +0000001011001010 +0000001011010001 +0000001011011000 +0000001011011111 +0000001011100110 +0000001011101101 +0000001011110100 +0000001011111011 +0000001100000010 +0000001100001001 +0000001100010000 +0000001100010111 +0000001100011110 +0000001100100101 +0000001100101100 +0000001100110011 +0000001100111010 +0000001101000001 +0000001101001000 +0000001101001111 +0000001101010110 +0000001101011101 +0000001101100100 +0000001101101011 +0000001101110010 +0000001101111001 +0000001110000000 +0000001110000111 +0000001110001110 +0000001110010101 +0000001110011100 +0000001110100011 +0000001110101010 +0000001110110001 +0000001110111000 +0000001110111111 +0000001111000110 +0000001111001101 +0000001111010100 +0000001111011011 +0000001111100010 +0000001111101001 +0000001111110000 +0000001111110111 +0000001111111110 +0000010000000101 +0000010000001100 +0000010000010011 +0000010000011010 +0000010000100001 +0000010000101000 +0000010000101111 +0000010000110110 +0000010000111101 +0000010001000100 +0000010001001011 +0000010001010010 +0000010001011001 +0000010001100000 +0000010001100111 +0000010001101110 +0000010001110101 +0000010001111100 +0000010010000011 +0000010010001010 +0000010010010001 +0000010010011000 +0000010010011111 +0000010010100110 +0000010010101101 +0000010010110100 +0000010010111011 +0000010011000010 +0000010011001001 +0000010011010000 +0000010011010111 +0000010011011110 +0000010011100101 +0000010011101100 +0000010011110011 +0000010011111010 +0000010100000001 +0000010100001000 +0000010100001111 +0000010100010110 +0000010100011101 +0000010100100100 +0000010100101011 +0000010100110010 +0000010100111001 +0000010101000000 +0000010101000111 +0000010101001110 +0000010101010101 +0000010101011100 +0000010101100011 +0000010101101010 +0000010101110001 +0000010101111000 +0000010101111111 +0000010110000110 +0000010110001101 +0000010110010100 +0000010110011011 +0000010110100010 +0000010110101001 +0000010110110000 +0000010110110111 +0000010110111110 +0000010111000101 +0000010111001100 +0000010111010011 +0000010111011010 +0000010111100001 +0000010111101000 +0000010111101111 +0000010111110110 +0000010111111101 +0000011000000100 +0000011000001011 +0000011000010010 +0000011000011001 +0000011000100000 +0000011000100111 +0000011000101110 +0000011000110101 +0000011000111100 +0000011001000011 +0000011001001010 +0000011001010001 +0000011001011000 +0000011001011111 +0000011001100110 +0000011001101101 +0000011001110100 +0000011001111011 +0000011010000010 +0000011010001001 +0000011010010000 +0000011010010111 +0000011010011110 +0000011010100101 +0000011010101100 +0000011010110011 +0000011010111010 +0000011011000001 +0000011011001000 +0000011011001111 +0000011011010110 +0000011011011101 +0000011011100100 +0000011011101011 +0000011011110010 +0000011011111001 +0000011100000000 +0000011100000111 diff --git a/tests/embedded_bram_slave/test.v b/tests/embedded_bram_slave/test.v new file mode 100644 index 0000000..0ee2833 --- /dev/null +++ b/tests/embedded_bram_slave/test.v @@ -0,0 +1,121 @@ +`default_nettype none + +`include "messages.vh" + +`ifndef MASTER_OPERATIONS_COUNT + `error_MASTER_OPERATIONS_COUNT_must_be_defined +; /* Cause syntax error */ +`endif + +`ifndef ROM_WORDS_COUNT + `error_ROM_WORDS_COUNT_must_be_defined +; /* Cause syntax error */ +`endif + +`ifndef SIMULATION + `error_SIMULATION_not_defined +; /* Cause syntax error */ +`endif + +module embedded_bram_test(); + wire M_ACK_I; + wire M_CLK_I; + wire [19:0] M_ADR_O; + wire [15:0] M_DAT_I; + wire [15:0] M_DAT_O; + wire M_RST_I; + wire M_STB_O; + wire M_CYC_O; + wire M_WE_O; + wire M_STALL_I; + + wire S_ACK_O; + wire S_CLK_I; + wire [8:0] S_ADR_I; + wire [15:0] S_DAT_I; + wire [15:0] S_DAT_O; + wire S_RST_I; + wire S_STB_I; + wire S_WE_I; + wire S_STALL_O; + + /* Non-wishbone */ + wire M_finished; + + master_model + #( + .MASTER_NR(0), + .OPERATIONS_FILE("operations.mem"), + .OPERATIONS_COUNT(`MASTER_OPERATIONS_COUNT) + ) master + ( + .ACK_I(M_ACK_I), + .CLK_I(M_CLK_I), + .ADR_O(M_ADR_O), + .DAT_I(M_DAT_I), + .DAT_O(M_DAT_O), + .RST_I(M_RST_I), + .STB_O(M_STB_O), + .CYC_O(M_CYC_O), + .WE_O(M_WE_O), + .STALL_I(M_STALL_I), + + .finished(M_finished) + ); + + embedded_bram_slave + #( + .MEMORY_BLOCKS(2), + .WORDS_TO_INITIALIZE(`ROM_WORDS_COUNT), + .INITIAL_CONTENTS_FILE("rom.mem") + ) slave + ( + .ACK_O(S_ACK_O), + .CLK_I(S_CLK_I), + .ADR_I(S_ADR_I), + .DAT_I(S_DAT_I), + .DAT_O(S_DAT_O), + .RST_I(S_RST_I), + .STB_I(S_STB_I), + .WE_I(S_WE_I), + .STALL_O(S_STALL_O) + ); + + reg CLK; + reg RST; + + assign M_ACK_I = S_ACK_O; + assign M_CLK_I = CLK; + assign M_DAT_I = S_DAT_O; + assign M_RST_I = RST; + assign M_STALL_I = S_STALL_O; + + assign S_CLK_I = CLK; + assign S_ADR_I = M_ADR_O[8:0]; /* Ignore 11 topmost bits */ + assign S_DAT_I = M_DAT_O; + assign S_RST_I = RST; + assign S_STB_I = M_STB_O && M_CYC_O; + assign S_WE_I = M_WE_O; + + integer i; + + initial begin + CLK <= 0; + RST <= 1; + + for (i = 0; i < 600; i++) begin + #1; + + CLK <= ~CLK; + + if (CLK) + RST <= 0; + + if (M_finished) + $finish; + end + + $display("error: master hasn't finished its operations in 300 ticks"); + $finish; + end +endmodule // embedded_bram_test |