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-rw-r--r--models/master.v8
1 files changed, 4 insertions, 4 deletions
diff --git a/models/master.v b/models/master.v
index 85656f3..1793fa8 100644
--- a/models/master.v
+++ b/models/master.v
@@ -1,6 +1,6 @@
/*
* A wishbone slave testing module (a "mock")
- *
+ *
* It performs a sequence of wishbone writes, reads and waits based on contents
* of provided .mem file. It prints error messages whenever the value it reads
* if different from the one it expects.
@@ -42,7 +42,7 @@ module master_model
parameter WORD_BITS = 8 * WORD_SIZE;
- parameter
+ parameter
OP_READ = 0,
OP_WRITE = 1,
OP_WAIT = 2, /* Keep CYC_O high, but STB_O low for 1 tick */
@@ -75,7 +75,7 @@ module master_model
j++;
end
-
+
if (operations[3*i][1:0] == OP_WRITE) begin
was_read[j] <= 0;
expected_data[j] <= {(8 * WORD_SIZE - 1){1'bx}};
@@ -112,7 +112,7 @@ module master_model
assign current_op_adr
= operations[3*operations_performed + 1][ADR_BITS - 1 : 0];
assign current_op_data
- = operations[3*operations_performed + 2][WORD_BITS - 1 : 0];
+ = operations[3*operations_performed + 2][WORD_BITS - 1 : 0];
assign operation_successful
= operations_performed < OPERATIONS_COUNT &&