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-rw-r--r--design/pins.pcf9
-rw-r--r--design/soc.v37
2 files changed, 36 insertions, 10 deletions
diff --git a/design/pins.pcf b/design/pins.pcf
index fabcd9c..7786c27 100644
--- a/design/pins.pcf
+++ b/design/pins.pcf
@@ -58,8 +58,7 @@ set_io sram_cs_n T6
set_io sram_oe_n L9
set_io sram_we_n T7
-# SPI to on-board chip
-#set_io sdo P12
-#set_io sdi P11
-#set_io sck R11
-#set_io ss_n R12
+set_io spi_sdo P12
+set_io spi_sdi P11
+set_io spi_sck R11
+set_io spi_ss_n R12
diff --git a/design/soc.v b/design/soc.v
index d4a5962..c7312f3 100644
--- a/design/soc.v
+++ b/design/soc.v
@@ -13,7 +13,12 @@
* h100A00 - h100A01 - VGA power-on register
* h100A02 - h100FFF - undefined (actually, repetitions of VGA power-on reg)
* h101000 - h17FFFF - undefined (actually, repetitions of VGA memory)
- * h180000 - h1FFFFF - read as 0, write as don't care
+ * h180000 - h1801FF - SPI data transfer memory
+ * h180200 - h180201 - SPI bytes_to_output reg
+ * h180202 - h180203 - SPI bytes_to_receive reg
+ * h180204 - h180207 - SPI operating reg
+ * h180208 - h1803FF - undefined (actually, repetitions of SPI regs)
+ * h180400 - h1FFFFF - undefined (actually, repetitions of SPI memory)
*/
`default_nettype none
@@ -43,6 +48,11 @@ module soc
output wire [2:0] vga_green,
output wire [2:0] vga_blue,
+ output wire spi_sdo,
+ input wire spi_sdi,
+ output wire spi_sck,
+ output wire spi_ss_n,
+
input wire button1,
input wire button2,
@@ -168,10 +178,27 @@ module soc
.blue(vga_blue)
);
- /* Slave 3 will be SPI controller, but for now - it's omitted */
- assign S3_ACK_O = 1;
- assign S3_DAT_O = 0;
- assign S3_STALL_O = 0;
+ spi_slave
+ #(
+ .MEMORY_BLOCKS(1)
+ ) slave3
+ (
+ .ACK_O(S3_ACK_O),
+ .CLK_I(CLK),
+ .ADR_I(S3_ADR_I[8:0]),
+ .DAT_I(S3_DAT_I),
+ .DAT_O(S3_DAT_O),
+ .RST_I(RST),
+ .STB_I(S3_STB_I),
+ .WE_I(S3_WE_I),
+ .STALL_O(S3_STALL_O),
+
+ /* Non-wishbone */
+ .sdo(spi_sdo),
+ .sdi(spi_sdi),
+ .sck(spi_sck),
+ .ss_n(spi_ss_n)
+ );
intercon intercon
(