diff options
Diffstat (limited to 'design/soc.v')
| -rw-r--r-- | design/soc.v | 69 |
1 files changed, 55 insertions, 14 deletions
diff --git a/design/soc.v b/design/soc.v index c7312f3..b395404 100644 --- a/design/soc.v +++ b/design/soc.v @@ -4,6 +4,9 @@ * slave 0 - embedded RAM (256x16) with memory initialized from file * slave 1 - SRAM * slave 2 - VGA text-mode controller + * slave 3 - SPI master controller + * slave 4 - UART controller (yet to be added) + * slave 5 - miscellaneous registers (yet to be added) * * The memory map from stack machine's viewpoint is as follows: * h000000 - h0001FF - embedded RAM @@ -12,13 +15,16 @@ * h100000 - h1009FF - VGA text memory * h100A00 - h100A01 - VGA power-on register * h100A02 - h100FFF - undefined (actually, repetitions of VGA power-on reg) - * h101000 - h17FFFF - undefined (actually, repetitions of VGA memory) - * h180000 - h1801FF - SPI data transfer memory - * h180200 - h180201 - SPI bytes_to_output reg - * h180202 - h180203 - SPI bytes_to_receive reg - * h180204 - h180207 - SPI operating reg - * h180208 - h1803FF - undefined (actually, repetitions of SPI regs) - * h180400 - h1FFFFF - undefined (actually, repetitions of SPI memory) + * h101000 - h13FFFF - undefined (actually, repetitions of VGA memory & regs) + * h140000 - h1401FF - SPI data transfer memory + * h140200 - h140201 - SPI bytes_to_output reg + * h140202 - h140203 - SPI bytes_to_receive reg + * h140204 - h140207 - SPI operating reg + * h140204 - h140207 - SPI operating reg + * h140208 - h1403FF - undefined (actually, repetitions of SPI regs) + * h140400 - h17FFFF - undefined (actually, repetitions of SPI memory & regs) + * h180000 - h1BFFFF - UART (not implemented yet) + * h1C0000 - h1FFFFF - miscellaneous peripherals (not implemented yet) */ `default_nettype none @@ -73,13 +79,20 @@ module soc wire M0_WE_O, M1_WE_O; wire M0_STALL_I, M1_STALL_I; - wire S0_ACK_O, S1_ACK_O, S2_ACK_O, S3_ACK_O; - wire [17:0] S0_ADR_I, S1_ADR_I, S2_ADR_I, S3_ADR_I; - wire [15:0] S0_DAT_I, S1_DAT_I, S2_DAT_I, S3_DAT_I; - wire [15:0] S0_DAT_O, S1_DAT_O, S2_DAT_O, S3_DAT_O; - wire S0_STB_I, S1_STB_I, S2_STB_I, S3_STB_I; - wire S0_WE_I, S1_WE_I, S2_WE_I, S3_WE_I; - wire S0_STALL_O, S1_STALL_O, S2_STALL_O, S3_STALL_O; + wire S0_ACK_O, S1_ACK_O, S2_ACK_O, + S3_ACK_O, S4_ACK_O, S5_ACK_O; + wire [17:0] S0_ADR_I, S1_ADR_I; + wire [16:0] S2_ADR_I, S3_ADR_I, S4_ADR_I, S5_ADR_I; + wire [15:0] S0_DAT_I, S1_DAT_I, S2_DAT_I, + S3_DAT_I, S4_DAT_I, S5_DAT_I; + wire [15:0] S0_DAT_O, S1_DAT_O, S2_DAT_O, + S3_DAT_O, S4_DAT_O, S5_DAT_O; + wire S0_STB_I, S1_STB_I, S2_STB_I, + S3_STB_I, S4_STB_I, S5_STB_I; + wire S0_WE_I, S1_WE_I, S2_WE_I, + S3_WE_I, S4_WE_I, S5_WE_I; + wire S0_STALL_O, S1_STALL_O, S2_STALL_O, + S3_STALL_O, S4_STALL_O, S5_STALL_O; wire CLK; wire RST; @@ -200,6 +213,18 @@ module soc .ss_n(spi_ss_n) ); + /* + * Slaves 4 and 5 will be UART controller and miscellaneous registers, + * but for now - they're omitted + */ + assign S4_ACK_O = 1; + assign S4_DAT_O = 0; + assign S4_STALL_O = 0; + + assign S5_ACK_O = 1; + assign S5_DAT_O = 0; + assign S5_STALL_O = 0; + intercon intercon ( .CLK(CLK), @@ -237,6 +262,22 @@ module soc .S3_WE_I(S3_WE_I), .S3_STALL_O(S3_STALL_O), + .S4_ACK_O(S4_ACK_O), + .S4_ADR_I(S4_ADR_I), + .S4_DAT_I(S4_DAT_I), + .S4_DAT_O(S4_DAT_O), + .S4_STB_I(S4_STB_I), + .S4_WE_I(S4_WE_I), + .S4_STALL_O(S4_STALL_O), + + .S5_ACK_O(S5_ACK_O), + .S5_ADR_I(S5_ADR_I), + .S5_DAT_I(S5_DAT_I), + .S5_DAT_O(S5_DAT_O), + .S5_STB_I(S5_STB_I), + .S5_WE_I(S5_WE_I), + .S5_STALL_O(S5_STALL_O), + .M0_ACK_I(M0_ACK_I), .M0_ADR_O(M0_ADR_O), .M0_DAT_I(M0_DAT_I), |