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-rw-r--r--src/example.v15
1 files changed, 10 insertions, 5 deletions
diff --git a/src/example.v b/src/example.v
index c83bea2..0609d69 100644
--- a/src/example.v
+++ b/src/example.v
@@ -320,8 +320,8 @@ module vga_timing(input wire clock_50mhz,
output reg h_sync,
output reg v_sync,
output reg display_on,
- output wire pixel_starting,
- output wire row_starting);
+ output reg pixel_starting,
+ output reg row_starting);
parameter h_pixels = 640;
parameter v_pixels = 480;
@@ -364,12 +364,16 @@ module vga_timing(input wire clock_50mhz,
h_sync <= ~h_pol;
v_sync <= ~v_pol;
display_on <= 0;
+ pixel_starting <= 0;
+ row_starting <= 0;
end // if (reset)
else begin
divider <= divider + 1;
if (divider == 1'b1) begin
display_on <= display_on_next_tick;
+ pixel_starting <= display_on_next_tick;
+ row_starting <= display_on_next_tick && h_counter == h_active_video_start - 1;
if (h_counter < h_frame_end - 1) begin
h_counter <= h_counter + 1;
@@ -389,11 +393,12 @@ module vga_timing(input wire clock_50mhz,
end // else: !if(v_counter < v_frame_end - 1)
end // else: !if(h_counter < h_frame_end - 1)
end // if (divider == 1'b1)
+ else begin
+ pixel_starting <= 0;
+ row_starting <= 0;
+ end
end // else: !if(reset)
end // always @ (posedge clock_50mhz)
-
- assign pixel_starting = display_on && divider == 1'b0;
- assign row_starting = pixel_starting && h_counter == h_active_video_start;
endmodule // vga_timing
module vga_pass_colors(input wire clock_50mhz,