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-rw-r--r--Makefile16
-rw-r--r--tclasm.tcl85
-rwxr-xr-xtests/stack_machine_store/instructions.s.tcl58
-rw-r--r--tests/stack_machine_store/test.v216
-rw-r--r--tests/stack_machine_store/words_to_verify.mem3
5 files changed, 377 insertions, 1 deletions
diff --git a/Makefile b/Makefile
index a1cc1b2..1f6cbce 100644
--- a/Makefile
+++ b/Makefile
@@ -32,6 +32,9 @@ STACK_MACHINE_OLD_TESTS := \
swap \
cond_jump
+STACK_MACHINE_TESTS := \
+ store
+
# Add other tests here if You need
TESTS := \
self \
@@ -42,7 +45,8 @@ TESTS := \
sram_slave \
embedded_bram_slave \
soc_simple_display \
- $(addprefix stack_machine_old_,$(STACK_MACHINE_OLD_TESTS))
+ $(addprefix stack_machine_old_,$(STACK_MACHINE_OLD_TESTS)) \
+ $(addprefix stack_machine_,$(STACK_MACHINE_TESTS))
# For each of these Makefile will attempt to generate VGAdump.ppm
# and compare it to VGAdump_expected.ppm inside that test's directory
@@ -149,6 +153,16 @@ tests/vga/test.vvp : tests/vga/test.v design/vga.v models/vga_display.v \
include/messages.vh
$(IV) $(IVFLAGS) -s vga_test $^ -o $@
+tests/stack_machine_%/test.vvp : \
+ tests/stack_machine_%/words_to_verify.mem \
+ tests/stack_machine_%/instructions.mem \
+ tests/stack_machine_%/test.v models/slave.v \
+ design/stack_machine.v include/messages.vh
+ $(IV) $(IVFLAGS) -s stack_machine_test \
+ -DINSTRUCTIONS_COUNT=$(call FILE_LINES,$(filter %ions.mem,$^)) \
+ -DWORDS_TO_VERIFY_COUNT=$(call FILE_LINES,$<) \
+ $(filter %.v,$^) -o $@
+
tests/stack_machine_old_%/test.vvp : \
tests/stack_machine_old_%/words_to_verify.mem \
tests/stack_machine_old_%/instructions.mem \
diff --git a/tclasm.tcl b/tclasm.tcl
index e69de29..27c92ae 100644
--- a/tclasm.tcl
+++ b/tclasm.tcl
@@ -0,0 +1,85 @@
+#!/bin/grep this[ ]script
+# this script is to be sourced, not executed by itself
+
+# procedures starting with "__" are internal and not to be used in asm code;
+# procedures starting with "_" are low-level procedures, that are not meant
+# to be directly used for code translated from webasm;
+# the rest are typical procedures webasm code will be mapped to
+
+proc __parse_binary {binary} {
+ set value 0
+
+ for {set bits_remaining $binary} \
+ {"$bits_remaining" != ""} \
+ {set bits_remaining [string range $bits_remaining 1 end]} {
+ set value [expr $value * 2]
+
+ if [string match 1* $bits_remaining] {
+ incr value
+ } elseif [string match 0* $bits_remaining] {
+ # nothing
+ } else {
+ error "'$binary' cannot be parsed as a binary number"
+ }
+ }
+
+ return $value
+}
+
+proc __parse_number {number} {
+ if [string match h?* $number] {
+ set value 0x[string range $number 1 end]
+ } elseif [string match b?* $number] {
+ set value [__parse_immutables-0.2.tar.gz  immutables-0.2.zip  
Elvis Pranskevichus7 years
generated by cgit
ss='add'>+
+proc __to_binary {number length} {
+ set value [__parse_number $number]
+
+ if {$value >= 2 ** $length ||
+ $value < -(2 ** ($length - 1))} {
+ error "value '$number' doesn't fit into $length bits"
+ }
+
+ for {set result ""} {$length > 0} {incr length -1} {
+ set result [expr $value % 2]$result
+ set value [expr $value >> 1]
+ }
+
+ return $result
+}
+
+proc _im {value} {
+ puts 1[__to_binary $value 15]
+}
+
+proc _const {value} {
+ puts 010100000[__to_binary $value 7]
+}
+
+proc _store {address_part} {
+ puts 011111100[__to_binary $address_part 7]
+}
+
+proc _store+ {address_part} {
+ puts 011011100[__to_binary $address_part 7]
+}
+
+proc _set_sp {address_part} {
+ puts 010000000[__to_binary $address_part 7]
+}
+
+proc halt {} {
+ puts 0000000000000000
+}
diff --git a/tests/stack_machine_store/instructions.s.tcl b/tests/stack_machine_store/instructions.s.tcl
new file mode 100755
index 0000000..f35461d
--- /dev/null
+++ b/tests/stack_machine_store/instructions.s.tcl
@@ -0,0 +1,58 @@
+#!/usr/bin/env tclsh
+
+source tclasm.tcl
+
+### simple test - write value hDEADBEEF to address h3ABCD;
+### then, write value h900DDEED to address FFBCE, but use operand addressing
+### (i.e. with hFFBBD in im and h00011 in r0)
+
+## get address h0 into sp
+_set_sp 0
+
+## get value hDEADBEEF into r1
+# DDDD EEEE AA
+# bits 31:22 of hDEADBEEF are 1101 1110 10
+_im b1101111010
+# AA DDDD BBBB EEEE E
+# bits 21:7 of hDEADBEEF are 10 1101 1011 1110 1
+_im b101101101111101
+# EEE FFFF
+# bits 6:0 of hDEADBEEF are 110 1111
+_const b1101111
+
+
+## get address h3ABCD into im and write to memory
+# 33 AAAA BBBB C
+# bits 17:7 of h3ABCD are 11 1010 1011 1
+_im b11101010111
+# CCC DDDD
+# bits 6:0 of h3ABCD are 100 1101
+_store b1001101
+
+
+## get value h00011 into r1
+# 111 1111
+# bits 6:0 of h00011 are 001 0001
+_const b0010001
+
+## get value h900DDEED into r1
+# 9999 0000 00
+# bits 31:22 of h900DDEED are 1001 0000 00
+_im b1001000000
+# 00 DDDD DDDD EEEE E
+# bits 21:7 of h900DDEED are 00 1101 1101 1110 1
+_im b001101110111101
+# EEE DDDD
+# bits 6:0 of h900DDEED are 110 1101
+_const b1101101
+
+## get address hFFBBD into im and write to memory
+# FFFF FFFF BBBB B
+# bits 19:7 of hFFBBD are 1111 1111 1011 1
+_im b1111111110111
+# BBB DDDD
+# bits 6:0 of hFFBBD are 011 1101
+_store+ b0111101
+
+## finish test
+halt
diff --git a/tests/stack_machine_store/test.v b/tests/stack_machine_store/test.v
new file mode 100644
index 0000000..d7e6be6
--- /dev/null
+++ b/tests/stack_machine_store/test.v
@@ -0,0 +1,216 @@
+`default_nettype none
+
+`include "messages.vh"
+
+`ifndef SIMULATION
+ `error_SIMULATION_not_defined
+; /* Cause syntax error */
+`endif
+
+`ifndef INSTRUCTIONS_COUNT
+ `error_INSTRUCTIONS_COUNT_must_be_defined
+; /* Cause syntax error */
+`endif
+
+`ifndef WORDS_TO_VERIFY_COUNT
+ `error_WORDS_TO_VERIFY_COUNT_must_be_defined
+; /* Cause syntax error */
+`endif
+
+module stack_machine_test();
+ wire M_CLK_I;
+ wire M_RST_I;
+
+ wire MI_ACK_I;
+
+ wire [19:0] MI_ADR_O;
+ wire [15:0] MI_DAT_I;
+ wire [15:0] MI_DAT_O;
+ wire MI_STB_O;
+ wire MI_CYC_O;
+ wire MI_WE_O;
+ wire MI_STALL_I;
+
+ wire MD_ACK_I;
+ wire MD_ERR_I;
+ wire [20:0] MD_ADR_O;
+ wire [31:0] MD_DAT_I;
+ wire [31:0] MD_DAT_O;
+ wire [3:0] MD_SEL_O; /* Ignored for now */
+ wire MD_STB_O;
+ wire MD_CYC_O;
+ wire MD_WE_O;
+ wire MD_STALL_I;
+
+ /* For simple tests we'll use separate slaves for instructions and data */
+ wire SI_ACK_O;
+ wire SI_CLK_I;
+ wire [19:0] SI_ADR_I;
+ wire [15:0] SI_DAT_I;
+ wire [15:0] SI_DAT_O;
+ wire SI_RST_I;
+ wire SI_STB_I;
+ wire SI_WE_I;
+ wire SI_STALL_O;
+
+ wire SD_ACK_O;
+ wire SD_CLK_I;
+ wire [20:0] SD_ADR_I;
+ wire [31:0] SD_DAT_I;
+ wire [31:0] SD_DAT_O;
+ wire SD_RST_I;
+ wire SD_STB_I;
+ wire SD_WE_I;
+ wire SD_STALL_O;
+
+ /* Non-wishbone */
+ wire M_finished;
+
+ stack_machine_new stack_machine
+ (
+ .CLK_I(M_CLK_I),
+ .RST_I(M_RST_I),
+
+ /* Instruction reading interface */
+ .I_ACK_I(MI_ACK_I),
+ .I_ADR_O(MI_ADR_O),
+ .I_DAT_I(MI_DAT_I),
+ .I_DAT_O(MI_DAT_O),
+ .I_STB_O(MI_STB_O),
+ .I_CYC_O(MI_CYC_O),
+ .I_WE_O(MI_WE_O),
+ .I_STALL_I(MI_STALL_I),
+
+ /* Data interface */
+ .D_ACK_I(MD_ACK_I),
+ .D_ERR_I(MD_ERR_I),
+ .D_ADR_O(MD_ADR_O),
+ .D_DAT_I(MD_DAT_I),
+ .D_DAT_O(MD_DAT_O),
+ .D_SEL_O(MD_SEL_O),
+ .D_STB_O(MD_STB_O),
+ .D_CYC_O(MD_CYC_O),
+ .D_WE_O(MD_WE_O),
+ .D_STALL_I(MD_STALL_I),
+
+ .finished(M_finished)
+ );
+
+ memory_slave_model
+ #(
+ .SLAVE_NR(0),
+ .WORD_SIZE(2),
+ .ADR_BITS(20),
+ .WRITABLE(0),
+ .WORDS_TO_INITIALIZE(`INSTRUCTIONS_COUNT),
+ .INITIAL_CONTENTS_FILE("instructions.mem")
+ ) slave_I
+ (
+ .ACK_O(SI_ACK_O),
+ .CLK_I(SI_CLK_I),
+ .ADR_I(SI_ADR_I),
+ .DAT_I(SI_DAT_I),
+ .DAT_O(SI_DAT_O),
+ .RST_I(SI_RST_I),
+ .STB_I(SI_STB_I),
+ .WE_I(SI_WE_I),
+ .STALL_O(SI_STALL_O)
+ );
+
+ memory_slave_model
+ #(
+ .SLAVE_NR(1),
+ .WORD_SIZE(4),
+ .ADR_BITS(21),
+ .WRITABLE(1),
+ .WORDS_TO_INITIALIZE(`INSTRUCTIONS_COUNT),
+ .INITIAL_CONTENTS_FILE("instructions.mem")
+ ) slave_D
+ (
+ .ACK_O(SD_ACK_O),
+ .CLK_I(SD_CLK_I),
+ .ADR_I(SD_ADR_I),
+ .DAT_I(SD_DAT_I),
+ .DAT_O(SD_DAT_O),
+ .RST_I(SD_RST_I),
+ .STB_I(SD_STB_I),
+ .WE_I(SD_WE_I),
+ .STALL_O(SD_STALL_O)
+ );
+
+ reg CLK;
+ reg RST;
+
+ assign M_CLK_I = CLK;
+ assign M_RST_I = RST;
+
+ assign MI_ACK_I = SI_ACK_O;
+ assign MI_DAT_I = SI_DAT_O;
+ assign MI_STALL_I = SI_STALL_O;
+
+ assign MD_ACK_I = SD_ACK_O;
+ assign MD_DAT_I = SD_DAT_O;
+ assign MD_STALL_I = SD_STALL_O;
+
+ assign SI_CLK_I = CLK;
+ assign SI_ADR_I = MI_ADR_O;
+ assign SI_DAT_I = MI_DAT_O;
+ assign SI_RST_I = RST;
+ assign SI_STB_I = MI_STB_O && MI_CYC_O;
+ assign SI_WE_I = MI_WE_O;
+
+ assign SD_CLK_I = CLK;
+ assign SD_ADR_I = MD_ADR_O;
+ assign SD_DAT_I = MD_DAT_O;
+ assign SD_RST_I = RST;
+ assign SD_STB_I = MD_STB_O && MD_CYC_O;
+ assign SD_WE_I = MD_WE_O;
+
+ integer i, j;
+ reg [21:0] address;
+ reg [31:0] expected_value;
+
+ reg [31:0] words_to_verify[`WORDS_TO_VERIFY_COUNT * 2 - 1 : 0];
+
+ initial begin
+ CLK <= 0;
+ RST <= 1;
+
+ for (i = 0; i < 3500; i++) begin
+ #1;
+
+ CLK <= ~CLK;
+
+ if (CLK) begin
+ RST <= 0;
+ `DBG(("step: %0d D_DAT_I: %x D_STB_O: %d D_CYC_O: %d D_STALL_I: %d r0: %x r1: %x lsu: %b stu: %b dcc: %d",
+ stack_machine.step, MD_DAT_I, MD_STB_O, MD_CYC_O, MD_STALL_I,
+ stack_machine.r0, stack_machine.r1,
+ stack_machine.load_store_uncompleted,
+ stack_machine.stack_transfer_uncompleted,
+ stack_machine.data_command_completes,
+ ));
+ end
+
+ if (M_finished) begin
+ $readmemh("words_to_verify.mem", words_to_verify,
+ 0, `WORDS_TO_VERIFY_COUNT * 2 - 1);
+
+ for (j = 0; j < `WORDS_TO_VERIFY_COUNT; j++) begin
+ /* Keep in mind we haven't implemented byte-grained access yet */
+ address = words_to_verify[2 * j][21:0];
+ expected_value = words_to_verify[2 * j + 1];
+ if (slave_D.memory[address] !== expected_value) begin
+ `MSG(("error: expected h%x at h%x, but got h%x",
+ expected_value, address, slave_D.memory[address]));
+ end
+ end
+
+ $finish;
+ end // if (M_finished)
+ end // for (i = 0; i < 3500; i++)
+
+ $display("error: cpu hasn't finished its operations in 1750 ticks");
+ $finish;
+ end // initial begin
+endmodule // stack_machine_test
diff --git a/tests/stack_machine_store/words_to_verify.mem b/tests/stack_machine_store/words_to_verify.mem
new file mode 100644
index 0000000..e23e491
--- /dev/null
+++ b/tests/stack_machine_store/words_to_verify.mem
@@ -0,0 +1,3 @@
+// address value
+ 3ABCD DEADBEEF
+ FFBCE 900DDEED
generated by cgit