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-rw-r--r--Makefile8
-rw-r--r--models/sram.v101
l---------tests/sram_slave/operations.memv1
-rw-r--r--tests/sram_slave/test.v136
4 files changed, 246 insertions, 0 deletions
diff --git a/Makefile b/Makefile
index b6d4841..6e9d578 100644
--- a/Makefile
+++ b/Makefile
@@ -29,6 +29,7 @@ TESTS := \
intercon \
div \
vga \
+ sram_slave \
$(addprefix stack_machine_,$(STACK_MACHINE_TESTS))
# For each of these Makefile will attempt to generate VGAdump.ppm
@@ -74,6 +75,13 @@ tests/self/test.vvp : tests/self/operations.mem tests/self/test.v \
-DMASTER_OPERATIONS_COUNT=$(call FILE_LINES,$<) \
$(filter %.v,$^) -o $@
+tests/sram_slave/test.vvp : tests/sram_slave/operations.mem \
+ tests/sram_slave/test.v models/sram.v models/master.v \
+ design/sram_slave.v include/messages.vh
+ $(IV) $(IVFLAGS) -s sram_slave_test \
+ -DMASTER_OPERATIONS_COUNT=$(call FILE_LINES,$<) \
+ $(filter %.v,$^) -o $@
+
tests/intercon/test.vvp : tests/intercon/operations.mem tests/intercon/test.v \
models/slave.v models/master.v design/intercon.v \
include/messages.vh
diff --git a/models/sram.v b/models/sram.v
new file mode 100644
index 0000000..5d1c707
--- /dev/null
+++ b/models/sram.v
@@ -0,0 +1,101 @@
+`default_nettype none
+`timescale 1ns/1ns
+
+`include "messages.vh"
+
+`ifndef SIMULATION
+ `error_SIMULATION_not_defined
+; /* Cause syntax error */
+`endif
+
+module K6R4016V1D_TC10_sram
+ (
+ input wire [17:0] sram_addr,
+ inout wire [15:0] sram_io,
+
+ input wire sram_cs_not,
+ input wire sram_oe_not,
+ input wire sram_we_not
+ );
+
+ reg [15:0] memory [2 ** 18 - 1 : 0];
+
+ wire enabled;
+ wire read;
+ wire write;
+
+ assign enabled = !sram_cs_not;
+ assign read = enabled && !sram_oe_not && sram_we_not;
+ assign write = enabled && !sram_we_not;
+
+ integer enabled_time;
+ integer read_time;
+ integer write_time;
+
+ reg [17:0] addr_last;
+
+ wire addr_unchanged;
+ assign addr_unchanged = addr_last == sram_addr;
+ integer addr_unchanged_time;
+
+ initial begin
+ enabled_time <= 0;
+ read_time <= 0;
+ write_time <= 0;
+
+ addr_unchanged_time <= 0;
+ end
+
+ reg [15:0] output_data;
+ reg outputting;
+ assign sram_io = outputting ? output_data : 16'hZZZZ;
+
+ always #1 begin
+ enabled_time <= enabled ? enabled_time + 1 : 0;
+ write_time <= write ? write_time + 1 : 0;
+ read_time <= read ? read_time + 1 : 0;
+
+ addr_last <= sram_addr;
+
+ if (!read && read_time > 0 && read_time < 8)
+ `MSG(("SRAM: error: output enable signal active for only %dns",
+ read_time));
+
+ if (!write && write_time > 0 && write_time < 9)
+ `MSG(("SRAM: error: write enable signal active for only %dns",
+ write_time));
+
+ if (((read && read_time) || (write && write_time)) && addr_unchanged)
+ addr_unchanged_time <= addr_unchanged_time + 1;
+ else
+ addr_unchanged_time <= 0;
+
+ if (write && write_time) begin
+ if (addr_unchanged) begin
+ if (write_time >= 9 && addr_unchanged_time >= 8) begin
+ memory[sram_addr] <= sram_io;
+
+ if (write_time == 9)
+ `DBG(("SRAM: write of h%x at h%x", sram_io, sram_addr));
+ end
+ end else begin
+ `MSG(("SRAM: error: address changed during write"));
+ end
+ end
+
+ if (read && read_time >= 8) begin
+ outputting <= 1;
+
+ if (addr_unchanged_time >= 7) begin
+ output_data <= memory[sram_addr];
+
+ if (addr_unchanged_time == 7)
+ `DBG(("SRAM: read of h%x at h%x", memory[sram_addr], sram_addr));
+ end else begin
+ output_data <= 16'hXXXX;
+ end
+ end else begin
+ outputting <= 0;
+ end
+ end // always #1
+endmodule // K6R4016V1D_TC10_sram
diff --git a/tests/sram_slave/operations.memv b/tests/sram_slave/operations.memv
new file mode 120000
index 0000000..68754d0
--- /dev/null
+++ b/tests/sram_slave/operations.memv
@@ -0,0 +1 @@
+../self/operations.memv \ No newline at end of file
diff --git a/tests/sram_slave/test.v b/tests/sram_slave/test.v
new file mode 100644
index 0000000..5e13251
--- /dev/null
+++ b/tests/sram_slave/test.v
@@ -0,0 +1,136 @@
+`default_nettype none
+`timescale 1ns/1ns
+
+`include "messages.vh"
+
+`ifndef MASTER_OPERATIONS_COUNT
+ `error_MASTER_OPERATIONS_COUNT_must_be_defined
+; /* Cause syntax error */
+`endif
+
+`ifndef SIMULATION
+ `error_SIMULATION_not_defined
+; /* Cause syntax error */
+`endif
+
+module sram_slave_test();
+ /* sram chip pins */
+ wire [17:0] sram_addr;
+ wire [15:0] sram_io;
+ wire sram_cs_not;
+ wire sram_oe_not;
+ wire sram_we_not;
+
+ /* slave wishbone interface */
+ wire S_ACK_O;
+ wire S_CLK_I;
+ wire [17:0] S_ADR_I;
+ wire [15:0] S_DAT_I;
+ wire [15:0] S_DAT_O;
+ wire S_RST_I;
+ wire S_STB_I;
+ wire S_WE_I;
+ wire S_STALL_O;
+
+ /* master wishbone interface */
+ wire M_ACK_I;
+ wire M_CLK_I;
+ wire [19:0] M_ADR_O;
+ wire [15:0] M_DAT_I;
+ wire [15:0] M_DAT_O;
+ wire M_RST_I;
+ wire M_STB_O;
+ wire M_CYC_O;
+ wire M_WE_O;
+ wire M_STALL_I;
+
+ /* Non-wishbone */
+ wire M_finished;
+
+ master_model
+ #(
+ .MASTER_NR(0),
+ .OPERATIONS_FILE("operations.mem"),
+ .OPERATIONS_COUNT(`MASTER_OPERATIONS_COUNT)
+ ) master
+ (
+ .ACK_I(M_ACK_I),
+ .CLK_I(M_CLK_I),
+ .ADR_O(M_ADR_O),
+ .DAT_I(M_DAT_I),
+ .DAT_O(M_DAT_O),
+ .RST_I(M_RST_I),
+ .STB_O(M_STB_O),
+ .CYC_O(M_CYC_O),
+ .WE_O(M_WE_O),
+ .STALL_I(M_STALL_I),
+
+ .finished(M_finished)
+ );
+
+ K6R4016V1D_TC10_sram sram
+ (
+ .sram_addr(sram_addr),
+ .sram_io(sram_io),
+ .sram_cs_not(sram_cs_not),
+ .sram_oe_not(sram_oe_not),
+ .sram_we_not(sram_we_not)
+ );
+
+ sram_wb_slave slave
+ (
+ .sram_addr(sram_addr),
+ .sram_io(sram_io),
+ .sram_cs_n(sram_cs_not),
+ .sram_oe_n(sram_oe_not),
+ .sram_we_n(sram_we_not),
+
+ .ACK_O(S_ACK_O),
+ .CLK_I(S_CLK_I),
+ .ADR_I(S_ADR_I),
+ .DAT_I(S_DAT_I),
+ .DAT_O(S_DAT_O),
+ .RST_I(S_RST_I),
+ .STB_I(S_STB_I),
+ .WE_I(S_WE_I),
+ .STALL_O(S_STALL_O)
+ );
+
+ reg CLK;
+ reg RST;
+
+ assign M_ACK_I = S_ACK_O;
+ assign M_CLK_I = CLK;
+ assign M_DAT_I = S_DAT_O;
+ assign M_RST_I = RST;
+ assign M_STALL_I = S_STALL_O;
+
+ assign S_CLK_I = CLK;
+ assign S_ADR_I = M_ADR_O[17:0]; /* Ignore 2 topmost bits */
+ assign S_DAT_I = M_DAT_O;
+ assign S_RST_I = RST;
+ assign S_STB_I = M_STB_O && M_CYC_O;
+ assign S_WE_I = M_WE_O;
+
+ integer i;
+
+ initial begin
+ CLK <= 0;
+ RST <= 1;
+
+ for (i = 0; i < 600; i++) begin
+ #7;
+
+ CLK <= ~CLK;
+
+ if (CLK)
+ RST <= 0;
+
+ if (M_finished)
+ $finish;
+ end
+
+ $display("error: master hasn't finished its operations in 300 ticks");
+ $finish;
+ end
+endmodule // sram_wb_slave_test