diff options
| -rw-r--r-- | Makefile | 10 | ||||
| -rw-r--r-- | design/slave_dispatcher.v (renamed from design/intercon.v) | 90 | ||||
| -rw-r--r-- | tests/slave_dispatcher/operations.memv (renamed from tests/intercon/operations.memv) | 0 | ||||
| -rw-r--r-- | tests/slave_dispatcher/test.v (renamed from tests/intercon/test.v) | 85 |
4 files changed, 77 insertions, 108 deletions
@@ -49,7 +49,7 @@ STACK_MACHINE_TESTS := \ TESTS := \ self \ self_32bit_word \ - intercon \ + slave_dispatcher \ div \ vga \ sram_slave \ @@ -147,10 +147,10 @@ tests/sram_slave/test.vvp : tests/sram_slave/operations.mem \ -DMASTER_OPERATIONS_COUNT=$(call FILE_LINES,$<) \ $(filter %.v,$^) -o $@ -tests/intercon/test.vvp : tests/intercon/operations.mem tests/intercon/test.v \ - models/slave.v models/master.v design/intercon.v \ - include/messages.vh - $(IV) $(IVFLAGS) -s intercon_test \ +tests/slave_dispatcher/test.vvp : tests/slave_dispatcher/operations.mem \ + tests/slave_dispatcher/test.v models/slave.v models/master.v \ + design/slave_dispatcher.v include/messages.vh + $(IV) $(IVFLAGS) -s slave_dispatcher_test \ -DMASTER_OPERATIONS_COUNT=$(call FILE_LINES,$<) \ $(filter %.v,$^) -o $@ diff --git a/design/intercon.v b/design/slave_dispatcher.v index bf908af..8cd0022 100644 --- a/design/intercon.v +++ b/design/slave_dispatcher.v @@ -1,60 +1,49 @@ `default_nettype none -module intercon +module slave_dispatcher ( input wire CLK, input wire RST, input wire S0_ACK_O, - output wire S0_CLK_I, output wire [17:0] S0_ADR_I, output wire [15:0] S0_DAT_I, input wire [15:0] S0_DAT_O, - output wire S0_RST_I, output wire S0_STB_I, output wire S0_WE_I, input wire S0_STALL_O, input wire S1_ACK_O, - output wire S1_CLK_I, output wire [17:0] S1_ADR_I, output wire [15:0] S1_DAT_I, input wire [15:0] S1_DAT_O, - output wire S1_RST_I, output wire S1_STB_I, output wire S1_WE_I, input wire S1_STALL_O, input wire S2_ACK_O, - output wire S2_CLK_I, output wire [17:0] S2_ADR_I, output wire [15:0] S2_DAT_I, input wire [15:0] S2_DAT_O, - output wire S2_RST_I, output wire S2_STB_I, output wire S2_WE_I, input wire S2_STALL_O, input wire S3_ACK_O, - output wire S3_CLK_I, output wire [17:0] S3_ADR_I, output wire [15:0] S3_DAT_I, input wire [15:0] S3_DAT_O, - output wire S3_RST_I, output wire S3_STB_I, output wire S3_WE_I, input wire S3_STALL_O, - output wire M_ACK_I, - output wire M_CLK_I, - input wire [19:0] M_ADR_O, - input wire [15:0] M_DAT_O, - output wire [15:0] M_DAT_I, - output wire M_RST_I, - input wire M_STB_O, - input wire M_CYC_O, - input wire M_WE_O, - output wire M_STALL_I + output wire S_COMBINED_ACK_O, + input wire [19:0] S_COMBINED_ADR_I, + input wire [15:0] S_COMBINED_DAT_O, + output wire [15:0] S_COMBINED_DAT_I, + input wire S_COMBINED_STB_I, + input wire S_COMBINED_WE_I, + output wire S_COMBINED_STALL_O ); wire [0:3] acks; @@ -70,22 +59,21 @@ module intercon reg [1:0] commands_awaiting; reg [1:0] slave_last_accessed; - wire operation_requested; wire working; wire [1:0] slave_accessed; - wire slave_switch; + wire slave_switch; wire [1:0] commands_awaiting_next_tick; - assign operation_requested = M_STB_O && M_CYC_O; - assign working = commands_awaiting || operation_requested; + assign working = commands_awaiting || S_COMBINED_STB_I; assign slave_accessed = commands_awaiting ? slave_last_accessed : - M_ADR_O[19:18]; - assign M_ACK_I = acks[slave_accessed] && working; - assign M_DAT_I = datas[slave_accessed]; - assign slave_switch = slave_accessed != M_ADR_O[19:18]; - assign M_STALL_I = stalls[slave_accessed] || slave_switch || - (commands_awaiting == 3 && !M_ACK_I); + S_COMBINED_ADR_I[19:18]; + assign S_COMBINED_ACK_O = acks[slave_accessed] && working; + assign S_COMBINED_DAT_O = datas[slave_accessed]; + assign slave_switch = slave_accessed != S_COMBINED_ADR_I[19:18]; + assign S_COMBINED_STALL_O = stalls[slave_accessed] || slave_switch || + (commands_awaiting == 3 && !S_COMBINED_ACK_O); assign commands_awaiting_next_tick - = commands_awaiting - M_ACK_I + (operation_requested && !M_STALL_I); + = commands_awaiting - S_COMBINED_ACK_O + + (S_COMBINED_STB_I && !S_COMBINED_STALL_O); `ifdef SIMULATION /* anything could be latched here, this is just to avoid undefined values */ @@ -104,39 +92,27 @@ module intercon commands_awaiting <= commands_awaiting_next_tick; end - assign S0_CLK_I = CLK; - assign S1_CLK_I = CLK; - assign S2_CLK_I = CLK; - assign S3_CLK_I = CLK; - assign M_CLK_I = CLK; + assign S0_ADR_I = S_COMBINED_ADR_I[17:0]; + assign S1_ADR_I = S_COMBINED_ADR_I[17:0]; + assign S2_ADR_I = S_COMBINED_ADR_I[17:0]; + assign S3_ADR_I = S_COMBINED_ADR_I[17:0]; - assign S0_RST_I = RST; - assign S1_RST_I = RST; - assign S2_RST_I = RST; - assign S3_RST_I = RST; - assign M_RST_I = RST; - - assign S0_ADR_I = M_ADR_O[17:0]; - assign S1_ADR_I = M_ADR_O[17:0]; - assign S2_ADR_I = M_ADR_O[17:0]; - assign S3_ADR_I = M_ADR_O[17:0]; - - assign S0_DAT_I = M_DAT_O; - assign S1_DAT_I = M_DAT_O; - assign S2_DAT_I = M_DAT_O; - assign S3_DAT_I = M_DAT_O; + assign S0_DAT_I = S_COMBINED_DAT_I; + assign S1_DAT_I = S_COMBINED_DAT_I; + assign S2_DAT_I = S_COMBINED_DAT_I; + assign S3_DAT_I = S_COMBINED_DAT_I; wire pass_strobe; - assign pass_strobe = operation_requested && !slave_switch && - (commands_awaiting != 3 || M_ACK_I); + assign pass_strobe = S_COMBINED_STB_I && !slave_switch && + (commands_awaiting != 3 || S_COMBINED_ACK_O); assign S0_STB_I = slave_accessed == 0 && pass_strobe; assign S1_STB_I = slave_accessed == 1 && pass_strobe; assign S2_STB_I = slave_accessed == 2 && pass_strobe; assign S3_STB_I = slave_accessed == 3 && pass_strobe; - assign S0_WE_I = M_WE_O; - assign S1_WE_I = M_WE_O; - assign S2_WE_I = M_WE_O; - assign S3_WE_I = M_WE_O; -endmodule // intercon + assign S0_WE_I = S_COMBINED_WE_I; + assign S1_WE_I = S_COMBINED_WE_I; + assign S2_WE_I = S_COMBINED_WE_I; + assign S3_WE_I = S_COMBINED_WE_I; +endmodule // slave_dispatcher diff --git a/tests/intercon/operations.memv b/tests/slave_dispatcher/operations.memv index 8785d5c..8785d5c 100644 --- a/tests/intercon/operations.memv +++ b/tests/slave_dispatcher/operations.memv diff --git a/tests/intercon/test.v b/tests/slave_dispatcher/test.v index 1945f44..d29b05c 100644 --- a/tests/intercon/test.v +++ b/tests/slave_dispatcher/test.v @@ -12,13 +12,14 @@ ; /* Cause syntax error */ `endif -module intercon_test(); +module slave_dispatcher_test(); + reg CLK; + reg RST; + wire M_ACK_I; - wire M_CLK_I; wire [19:0] M_ADR_O; wire [15:0] M_DAT_I; wire [15:0] M_DAT_O; - wire M_RST_I; wire M_STB_O; wire M_CYC_O; wire M_WE_O; @@ -34,8 +35,13 @@ module intercon_test(); wire S0_WE_I, S1_WE_I, S2_WE_I, S3_WE_I; wire S0_STALL_O, S1_STALL_O, S2_STALL_O, S3_STALL_O; - reg CLK; - reg RST; + wire S_COMBINED_ACK_O; + wire [19:0] S_COMBINED_ADR_I; + wire [15:0] S_COMBINED_DAT_I; + wire [15:0] S_COMBINED_DAT_O; + wire S_COMBINED_STB_I; + wire S_COMBINED_WE_I; + wire S_COMBINED_STALL_O; /* Non-wishbone */ wire M_finished; @@ -47,11 +53,11 @@ module intercon_test(); ) master ( .ACK_I(M_ACK_I), - .CLK_I(M_CLK_I), + .CLK_I(CLK), .ADR_O(M_ADR_O), .DAT_I(M_DAT_I), .DAT_O(M_DAT_O), - .RST_I(M_RST_I), + .RST_I(RST), .STB_O(M_STB_O), .CYC_O(M_CYC_O), .WE_O(M_WE_O), @@ -66,11 +72,11 @@ module intercon_test(); ) slave0 ( .ACK_O(S0_ACK_O), - .CLK_I(S0_CLK_I), + .CLK_I(CLK), .ADR_I(S0_ADR_I), .DAT_I(S0_DAT_I), .DAT_O(S0_DAT_O), - .RST_I(S0_RST_I), + .RST_I(RST), .STB_I(S0_STB_I), .WE_I(S0_WE_I), .STALL_O(S0_STALL_O) @@ -82,11 +88,11 @@ module intercon_test(); ) slave1 ( .ACK_O(S1_ACK_O), - .CLK_I(S1_CLK_I), + .CLK_I(CLK), .ADR_I(S1_ADR_I), .DAT_I(S1_DAT_I), .DAT_O(S1_DAT_O), - .RST_I(S1_RST_I), + .RST_I(RST), .STB_I(S1_STB_I), .WE_I(S1_WE_I), .STALL_O(S1_STALL_O) @@ -98,11 +104,11 @@ module intercon_test(); ) slave2 ( .ACK_O(S2_ACK_O), - .CLK_I(S2_CLK_I), + .CLK_I(CLK), .ADR_I(S2_ADR_I), .DAT_I(S2_DAT_I), .DAT_O(S2_DAT_O), - .RST_I(S2_RST_I), + .RST_I(RST), .STB_I(S2_STB_I), .WE_I(S2_WE_I), .STALL_O(S2_STALL_O) @@ -114,73 +120,71 @@ module intercon_test(); ) slave3 ( .ACK_O(S3_ACK_O), - .CLK_I(S3_CLK_I), + .CLK_I(CLK), .ADR_I(S3_ADR_I), .DAT_I(S3_DAT_I), .DAT_O(S3_DAT_O), - .RST_I(S3_RST_I), + .RST_I(RST), .STB_I(S3_STB_I), .WE_I(S3_WE_I), .STALL_O(S3_STALL_O) ); - intercon intercon + slave_dispatcher dispatcher ( .CLK(CLK), .RST(RST), .S0_ACK_O(S0_ACK_O), - .S0_CLK_I(S0_CLK_I), .S0_ADR_I(S0_ADR_I), .S0_DAT_I(S0_DAT_I), .S0_DAT_O(S0_DAT_O), - .S0_RST_I(S0_RST_I), .S0_STB_I(S0_STB_I), .S0_WE_I(S0_WE_I), .S0_STALL_O(S0_STALL_O), .S1_ACK_O(S1_ACK_O), - .S1_CLK_I(S1_CLK_I), .S1_ADR_I(S1_ADR_I), .S1_DAT_I(S1_DAT_I), .S1_DAT_O(S1_DAT_O), - .S1_RST_I(S1_RST_I), .S1_STB_I(S1_STB_I), .S1_WE_I(S1_WE_I), .S1_STALL_O(S1_STALL_O), .S2_ACK_O(S2_ACK_O), - .S2_CLK_I(S2_CLK_I), .S2_ADR_I(S2_ADR_I), .S2_DAT_I(S2_DAT_I), .S2_DAT_O(S2_DAT_O), - .S2_RST_I(S2_RST_I), .S2_STB_I(S2_STB_I), .S2_WE_I(S2_WE_I), .S2_STALL_O(S2_STALL_O), .S3_ACK_O(S3_ACK_O), - .S3_CLK_I(S3_CLK_I), .S3_ADR_I(S3_ADR_I), .S3_DAT_I(S3_DAT_I), .S3_DAT_O(S3_DAT_O), - .S3_RST_I(S3_RST_I), .S3_STB_I(S3_STB_I), .S3_WE_I(S3_WE_I), .S3_STALL_O(S3_STALL_O), - .M_ACK_I(M_ACK_I), - .M_CLK_I(M_CLK_I), - .M_ADR_O(M_ADR_O), - .M_DAT_O(M_DAT_O), - .M_DAT_I(M_DAT_I), - .M_RST_I(M_RST_I), - .M_STB_O(M_STB_O), - .M_CYC_O(M_CYC_O), - .M_WE_O(M_WE_O), - .M_STALL_I(M_STALL_I) + .S_COMBINED_ACK_O(S_COMBINED_ACK_O), + .S_COMBINED_ADR_I(S_COMBINED_ADR_I), + .S_COMBINED_DAT_I(S_COMBINED_DAT_I), + .S_COMBINED_DAT_O(S_COMBINED_DAT_O), + .S_COMBINED_STB_I(S_COMBINED_STB_I), + .S_COMBINED_WE_I(S_COMBINED_WE_I), + .S_COMBINED_STALL_O(S_COMBINED_STALL_O) ); + assign M_ACK_I = S_COMBINED_ACK_O; + assign M_DAT_I = S_COMBINED_DAT_O; + assign M_STALL_I = S_COMBINED_STALL_O; + + assign S_COMBINED_ADR_I = M_ADR_O; + assign S_COMBINED_DAT_I = M_DAT_O; + assign S_COMBINED_STB_I = M_STB_O && M_CYC_O; + assign S_COMBINED_WE_I = M_WE_O; + integer i; initial begin @@ -197,20 +201,9 @@ module intercon_test(); if (M_finished) $finish; - - /* - * I should delete this debugging code, but from time to time - * it proves so handy, that I just can't do it :/ - */ - // if (!CLK) - // `DBG(({"M_CYC_O: %d M_STB_O: %d M_ACK_I: %d M_STALL_I: %d ", - // "sla: %d sa: %d ca: %d RST: %b"}, - // M_CYC_O, M_STB_O, M_ACK_I, M_STALL_I, - // intercon.slave_last_accessed, intercon.slave_accessed, - // intercon.commands_awaiting, intercon.RST)); end $display("error: master hasn't finished its opertaions in 300 ticks"); $finish; end -endmodule // intercon_test +endmodule // slave_dispatcher_test |